다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Information Theory and Reliable Communication

Random number generators in digital information systems make use of physical entropy sources such as electronic and photonic noise to add unpredictability to deterministically generated pseudo-random sequences1,2. However, there is a large gap between the generation rates achieved with existing physical sources and the high data rates of many computation and communication systems; this is a fundamental weakness of these systems. Here we show that good quality random bit sequences can be generated at very fast bit rates using physical chaos in semiconductor lasers. Streams of bits that pass standard statistical tests for randomness have been generated at rates of up to 1.7 Gbps by sampling the fluctuating optical output of two chaotic lasers. This rate is an order of magnitude faster than that of previously reported devices for physical random bit generators with verified randomness. This means that the performance of random number generators can be greatly improved by using chaotic laser devices as physical entropy sources. Random-number generators are important in digital information systems. However, the speed at which current sources operate is much slower than the typical data rates used in communication and computing. Chaos in semiconductor lasers might help to bridge the gap.

Fast physical random bit generation with chaotic semiconductor lasers

The power consumed by a circuit varies according to the activity of its individual transistors and other components As a result, measurements of the power used by actual computers or microchips contain information about the operations being performed and the data being processed Cryptographic designs have traditionally assumed that secrets are manipulated in environments that expose no information beyond the specified inputs and outputs This paper examines how information leaked through power consumption and other side channels can be analyzed to extract secret keys from a wide range of devices The attacks are practical, non-invasive, and highly effective—even against complex and noisy systems where cryptographic computations account for only a small fraction of the overall power consumption We also introduce approaches for preventing DPA attacks and for building cryptosystems that remain secure even when implemented in hardware that leaks

/pdf/introduction-to-differential-power-analysis-3gzgydg5a4.pdf

Introduction to differential power analysis

Analogue IC Design: the Current Mode Approach

This paper presents a novel topology of ultra‐low voltage (ULV) operational transconductance amplifier (OTA), which exploits several design techniques to achieve high efficiency, symmetrical slew rate, good linearity, and robustness in spite of ultra‐low voltage operation. Simulations in a commercial 130‐nm CMOS technology with 0.3‐V supply voltage show the best reported small‐signal figure‐of‐merit among 0.3‐V OTAs, with a dc gain of 56.2 dB, a unity‐gain frequency of 26.2 kHz over a 150‐pF load capacitor, and a power consumption of 139.5 nW. A symmetrical slew rate of about 3.2 V/ms is achieved, and results are consistent under process, supply voltage and temperature variations, and device mismatches.

A body‐driven rail‐to‐rail 0.3 V operational transconductance amplifier exploiting current gain stages

A low-power class-AB Gm-C biquad stage has been designed using a voltage buffer based on error amplifiers and a push-pull current mirror. The class-AB architecture allows good power efficiency by lowering the required bias current. The biquad stage consumes $250\boldsymbol{\mu} \mathbf{A}$ from a 1.2V supply, and achieves a resonance frequency of 2.2MHz with a Q of 2. The SFDR (spurious-free dynamic range) with a two-tone test is 48dB and the SNR (signal-to-noise ratio) is 44.4dB, with a 400mVpp differential input signal. A pseudo-differential architecture allows large bandwidth and lower power consumption in the transconductance stages. The stage can be used to synthetize lowpass and bandpass filters composed of low-Q stages.

A low-power class-AB Gm-C biquad stage in CMOS 40nm technology

A phase detector receives an oscillating signal and a clock signal, and outputs a differential signal representing a phase difference therebetween. The phase detector includes a first differential pair of transistors respectively driven by the clock signal and by an inverted clock signal for generating the differential signal. An auxiliary differential pair of transistors is coupled to the first differential pair of transistors and is respectively driven by the oscillating signal and by an inverted oscillating signal. A current generator biases the first differential pair of transistors and the auxiliary differential pair of transistors.

Phase detector and method of generating a phase-shift differential signal

A GaAs monolithic clock and data recovery circuit for 2.5 Gb/s NRZ data stream has been designed and fabricated by using 0.3 mm HEMT technology from IAF FhG foundry. The main functions carried out by the IC are: signal amplification (25 dB), clock recovery and decision. The design is intended to achieve a complete 2.5 Gb/s receiver by using the IC and a LN preamplifier (transimpedance stage and limiting amplifier stage) placed in a DIL package. The overall scheme comprises about 200 active devices, used both for analog and digital blocks, uses a single rail bias (-4.5 V) and standard ECL output levels. The fabricated chip has been tested and measured by using a ceramic package and a small PCB, showing an input sensitivity of 30 mVpp and rms output jitter below 10 psec under 215-1 PRBS.

A monolithic GaAs clock and data recovery circuit for 2.5 Gb/s NRZ data stream

A technique to design narrowband amplifiers by using conditionally stable transistors is presented. The proposed analytical approach allows us to design lossless matching networks, by providing power matching at one port and minimum mismatch at the other port. The use of this technique leads to high gain as well as proper stability margins. © 2001 John Wiley & Sons, Inc. Microwave Opt Technol Lett 31: 208–210, 2001.

Alessandro Trifiletti

Papers

A body‐driven rail‐to‐rail 0.3 V operational transconductance amplifier exploiting current gain stages

A low-power class-AB Gm-C biquad stage in CMOS 40nm technology

Phase detector and method of generating a phase-shift differential signal

A monolithic GaAs clock and data recovery circuit for 2.5 Gb/s NRZ data stream

Design of narrowband amplifiers with conditionally stable transistors