다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Information Theory and Reliable Communication

Random number generators in digital information systems make use of physical entropy sources such as electronic and photonic noise to add unpredictability to deterministically generated pseudo-random sequences1,2. However, there is a large gap between the generation rates achieved with existing physical sources and the high data rates of many computation and communication systems; this is a fundamental weakness of these systems. Here we show that good quality random bit sequences can be generated at very fast bit rates using physical chaos in semiconductor lasers. Streams of bits that pass standard statistical tests for randomness have been generated at rates of up to 1.7 Gbps by sampling the fluctuating optical output of two chaotic lasers. This rate is an order of magnitude faster than that of previously reported devices for physical random bit generators with verified randomness. This means that the performance of random number generators can be greatly improved by using chaotic laser devices as physical entropy sources. Random-number generators are important in digital information systems. However, the speed at which current sources operate is much slower than the typical data rates used in communication and computing. Chaos in semiconductor lasers might help to bridge the gap.

Fast physical random bit generation with chaotic semiconductor lasers

The power consumed by a circuit varies according to the activity of its individual transistors and other components As a result, measurements of the power used by actual computers or microchips contain information about the operations being performed and the data being processed Cryptographic designs have traditionally assumed that secrets are manipulated in environments that expose no information beyond the specified inputs and outputs This paper examines how information leaked through power consumption and other side channels can be analyzed to extract secret keys from a wide range of devices The attacks are practical, non-invasive, and highly effective—even against complex and noisy systems where cryptographic computations account for only a small fraction of the overall power consumption We also introduce approaches for preventing DPA attacks and for building cryptosystems that remain secure even when implemented in hardware that leaks

/pdf/introduction-to-differential-power-analysis-3gzgydg5a4.pdf

Introduction to differential power analysis

Analogue IC Design: the Current Mode Approach

In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

/pdf/a-tree-based-architecture-for-high-performance-ultra-low-3sf66ewe.pdf

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Clock disabling for power management has been implemented in some microcontrollers, but the wake-up time of Xtal/PLL-based systems is incompatible with fast interrupt response. On the other hand, hardwired on-chip clocking has been used for dedicated circuits. We illustrate the design issues of a general-purpose microcontroller core with a programmable on-chip fully-digital clock generator. The CPU is compatible with the PIC16C57 instruction set and supports software-controlled clocking modes-ranging from 44 MHz up to 124 MHz; on-line self-tuning of the maximum full-speed frequency in case of peak-performance requirements; ultra-fast wake-up even with totally disabled clock generator-namely 8.6 ns.

A low-power microcontroller with on-chip self-tuning digital clock-generator for variable-load applications

New linear models to calibrate four-channel time-interleaved analog-to-digital converters are proposed and investigated. The ideal four-periodic correction filters, which cancel distortions, are computed as a function of the error filters that model the analog transfer function of each channel, including the sampling time. These correction filters are then approximated as a linear combination of base filters and new accurate models with a limited number of free parameters are proposed. Calibration is performed using the recursive least squares algorithm to estimate the coefficients of the linear combination (and the offset term). The resulting algorithms are tested for accuracy, convergence speed, and stability in a fixed-point implementation, and are compared with previously published linear background calibration techniques. The proposed filter bank significantly improves the accuracy/complexity tradeoff with respect to previously published techniques.

New Models for the Calibration of Four-Channel Time-Interleaved ADCs Using Filter Banks

A novel class-AB Flipped Voltage Follower is proposed, suitable for low-voltage low-power CMOS implementation in advanced technology nodes. Simulations have been performed using STMicroelectronics models for the 45nm technology. The Flipped Voltage Follower allows low output impedance and high linearity by means of a feedback loop. However, like the conventional common-drain voltage follower, it has class-A behavior. Class-AB behavior enables faster settling with large capacitive loads and/or lower power consumption.

A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier

The susceptibility of cryptographic devices to attacks based on power analysis can be both significantly and efficiently tested at early design steps. The results from a real case application show the advantages of the approach.

Alessandro Trifiletti

Papers

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

A low-power microcontroller with on-chip self-tuning digital clock-generator for variable-load applications

New Models for the Calibration of Four-Channel Time-Interleaved ADCs Using Filter Banks

A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier

Testing power-analysis attack susceptibility in register-transfer level designs