scispace - formally typeset
A

Atsushi Kurobe

Researcher at Toshiba

Publications -  68
Citations -  2425

Atsushi Kurobe is an academic researcher from Toshiba. The author has contributed to research in topics: Layer (electronics) & Electron mobility. The author has an hindex of 22, co-authored 68 publications receiving 2359 citations. Previous affiliations of Atsushi Kurobe include University of Tokyo.

Papers
More filters
Journal ArticleDOI

Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology

TL;DR: In this article, a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology is presented, and electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's.
Journal ArticleDOI

Analysis and application of theoretical gain curves to the design of multi-quantum-well lasers

TL;DR: In this article, the authors derived the gain/current curves for a single quantum well and the optimum well number, cavity length, threshold current, and current density of multi-quantum-well (MQW) lasers.
Patent

Si-SiGe semiconductor device and method of fabricating the same

TL;DR: A semiconductor device comprises a semiconductor substrate, a first semiconductor layer under compressive strain formed on the substrate, an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a region other than the predetermined region with an insulating film lying there between, wherein the insulators film has an opening and the first and second semiconductor layers are connected through the opening as mentioned in this paper.
Patent

Method of manufacturing a substrate using an SiGe layer

TL;DR: A semiconductor device comprises a base substrate, a silicon oxide layer, a first semiconductor layer formed on the base substrate and a gate electrode configured to induce a channel in a surface region of the second semiconductor layers.
Patent

Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same

TL;DR: In this article, a double-deck semiconductor nanocrystal consisting of a first semiconductor and a second semiconductor stacked one upon the other via a second insulating layer, and a third layer selectively formed on the first layer so as to cover the at least one double-deck semiconductor nano-nocrystal was constructed.