Journal ArticleDOI
Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology
TLDR
In this article, a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology is presented, and electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's.Abstract:
We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si/sub 0.9/Ge/sub 0.1/ layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer.read more
Citations
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Journal ArticleDOI
Si/SiGe heterostructures: from material and physics to devices and circuits
TL;DR: In this paper, the authors present a review of the material properties, growth techniques, band structure and the main electronic devices of the Si/SiGe heterostructure system, in particular, the important device technologies in mainstream microelectronics.
Journal ArticleDOI
Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness
TL;DR: In this paper, a six-band k⋅p model has been used to study the mobility of holes in Si inversion layers for different crystal orientations, for both compressive or tensile strain applied to the channel, and for a varying thickness of the Si layer.
Patent
Method for fabricating a semiconductor structure including a metal oxide interface with silicon
TL;DR: In this paper, a method of fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface, forming on the surface of the silicon substrate, by atomic layer deposition (ALD), a seed layer (20;20') characterised by a silicate material and forming, by ALD, one or more layers of a high dielectric constant oxide (40) on the seed layer.
Journal ArticleDOI
Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance
Shinichi Takagi,T. Iisawa,Tsutomu Tezuka,T. Numata,Shu Nakaharai,N. Hirashita,Yoshihiko Moriyama,Koji Usuda,Eiji Toyoda,Sanjeewa Dissanayake,Masato Shichijo,Ryosho Nakane,Satoshi Sugahara,Mitsuru Takenaka,Naoharu Sugiyama +14 more
TL;DR: In this article, the authors reviewed the recent approaches in realizing carrier-transport-enhanced CMOS, and the critical issues, fabrication techniques, and device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented.
References
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Journal ArticleDOI
On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Journal ArticleDOI
Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors
TL;DR: In this article, n-type metal-oxide-semiconductor field effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si/sub 1/spl minus/x/Ge/sub x/ standard MOS fabrication techniques were utilized, including thermal oxidation of the strained Si Surface channel devices show low-field mobility enhancements of 80% at room temperature and 12% at 10 K, when compared to control devices fabricated in Czochralski Si Similar enhancements are observed in the device transconductance
Electron Mobility Enhancement in S trained-Si N-Type Metal-Oxide- S emiconductor Field-Effect Transistors
TL;DR: In this paper, n-type metal-oxide-semiconductor field effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si1 -zGez were used.
Journal ArticleDOI
Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFET’s
R. Oberhuber,G. Zandler,P. Vogl +2 more
TL;DR: In this paper, the hole mobility of a strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated theoretically and compared with the mobility of conventional (unstrained) Si $p$-MOSFLT's.
Proceedings ArticleDOI
Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs
TL;DR: In this article, the hole mobility in surface-channel p-MOSFETs employing pseudomorphic, strained-Si layers is reported for the first time, where hole mobility enhancement is observed to increase roughly linearly with the strain as the Ge content in the relaxed Si/sub 1-x/Ge/sub x/ buffer layer increases.