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Logical Effort Designing Fast Cmos Circuits

The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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Analog to Digital Converters (ADC): A Literature Review

This article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc.

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix

A 5-bit 500MS/s flash ADC with temperature-compensated inverter-based comparators

The challenges in designing RF front-end blocks for IoT are designing low phase noise and low power consumption circuits. The voltage-controlled oscillator (VCO) is one of the vital blocks in determining the RF transceiver performance. In this work, a current reuse CMOS LC-tank VCO was implemented to achieve low power consumption and have the same performance as typical LC-tank VCO. This current reuse class-C VCO can display higher DC-RF current conversion efficiency and better overall performance than the typical class-C VCO. In this work, the current reuse class-C VCO has been implemented in 0.13-μm CMOS technology for Internet of Things (IoT) applications. The power consumption is 2.0432 mW, and its phase noise is -122.4 dBc/Hz@1MHz.

Design of 0.13-μm CMOS Voltage-Controlled Oscillator (VCO) for 2.45 GHz IoT Application

This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).

Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

This paper presents the design of a 6-bit scalable hybrid flash SAR (successive approximation register) analog-to-digital converter (ADC). The ADC has a scalable architecture because of the usage of an inverter based comparator. The conversion time is reduced by adopting a 3-bit/cycle approach. A segmented split-capacitor charge redistribution digital-to-analog converter (CDAC) is used to reduce the DAC settling time and the design area. The ADC is implemented in a 28 nm CMOS technology with the scalable V DD from 0.5 V to 1 V. The ADC operates from 10 MHz to 1.1 GHz for a V DD of 0.5 V to 1 V respectively. The design shows 47.7 fJ/conv-step and 29.56 fJ/conv-step for V DD of 0.9 V and 0.6 V respectively.

A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS

This paper presents the design of a frequency synthesizer using phase locked loop (PLL) in a standard 130 nm CMOS technology with the supply voltage of 1.2 V. The low power and the low phase noise based current reuse VCO (CRVCO) and the frequency divider have been used to design the frequency synthesizer. The designed CRVCO gives a low power and a low phase noise performance. The designed PLL consumes 0.52 mW of power with −141 dBc/Hz of phase noise at 10 MHz offset and FOM power of 1.33 mW/GHz. The PLL shows satisfactory performance for −40 °C to 125 °C with various process corners of transistors.

Design of a 0.52 mW −141 dBc/Hz and 450 MHz frequency synthesizer using low power and low phase noise current reuse VCO

In this paper, a low-power quadrature LC—oscillator using the current-reuse technique is presented. In the proposed topology, both the core-and-coupling currents are reused to reduce the power consumption. A quadrature LC-oscillator is designed in CMOS 65 nm technology for Bluetooth at 2.45 GHz. The oscillator consumes 2.8 mA of current from a 0.85 V supply voltage. The oscillator's simulated phase noise at 3 MHz offset from the 2.45 GHz center frequency is -130.162 dBc/Hz, resulting in a figure-of-merit (FoM) of 184.4 dB.

A Low-Power Quadrature LC-Oscillator Using Core-and-Coupling Current-Reuse

In this paper, we propose a new multiplexer-based frequency selector for designing area-efficient phase locked loop (PLL) for frequency synthesis. Such reduction in the design area has been achieved by replacing conventional capacitor array in voltage controlled oscillator of this PLL by multiplexor based frequency selector. Subsequently, it has been coupled with the current-reuse voltage-controlled oscillator to reduce overall phase noise of PLL to a considerable extent. Additionally, the proposed PLL circuitry is capable of self-bandwidth switching and it is suitable for applications requiring multiple frequency bands and fast settling time. Circuit implementation of this PLL performed at 130 nm-CMOS technology-node resulted in the design area of 0.037 mm2, power consumption of 360µW at 0.9 GHz and a settling time of 22 µS. In comparison with the state-of-the-art implementations, our design occupies 98% smaller area and consumes 50% lesser power.

B. Dinesh Kumar

Papers

Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS

Design of a 0.52 mW −141 dBc/Hz and 450 MHz frequency synthesizer using low power and low phase noise current reuse VCO

A Low-Power Quadrature LC-Oscillator Using Core-and-Coupling Current-Reuse

A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector