A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector

TLDR: A new multiplexer-based frequency selector for designing area-efficient phase locked loop (PLL) for frequency synthesis by replacing conventional capacitor array in voltage controlled oscillator by multiplexor based frequency selector, which occupies 98% smaller area and consumes 50% lesser power.

Abstract: In this paper, we propose a new multiplexer-based frequency selector for designing area-efficient phase locked loop (PLL) for frequency synthesis. Such reduction in the design area has been achieved by replacing conventional capacitor array in voltage controlled oscillator of this PLL by multiplexor based frequency selector. Subsequently, it has been coupled with the current-reuse voltage-controlled oscillator to reduce overall phase noise of PLL to a considerable extent. Additionally, the proposed PLL circuitry is capable of self-bandwidth switching and it is suitable for applications requiring multiple frequency bands and fast settling time. Circuit implementation of this PLL performed at 130 nm-CMOS technology-node resulted in the design area of 0.037 mm2, power consumption of 360µW at 0.9 GHz and a settling time of 22 µS. In comparison with the state-of-the-art implementations, our design occupies 98% smaller area and consumes 50% lesser power.