A nanowire array is described herein. The nanowire array comprises a substrate and a plurality of nanowires extending essentially vertically from the substrate; wherein: each of the nanowires has uniform chemical along its entire length; a refractive index of the nanowires is at least two times of a refractive index of a cladding of the nanowires. This nanowire array is useful as a photodetector, a submicron color filter, a static color display or a dynamic color display.

Light absorption and filtering properties of vertically oriented semiconductor nano wires

This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT ). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.

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Multi- $V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

The atomic layer etching (ALE) of Al2O3 was demonstrated using sequential, self-limiting thermal reactions with tin(II) acetylacetonate (Sn(acac)2) and hydrogen fluoride (HF) as the reactants. The Al2O3 samples were Al2O3 atomic layer deposition (ALD) films grown using trimethylaluminum and H2O. The HF source was HF-pyridine. Al2O3 was etched linearly with atomic level precision versus number of reactant cycles. The Al2O3 ALE was monitored at temperatures from 150 to 250 °C. Quartz crystal microbalance (QCM) studies revealed that the sequential Sn(acac)2 and HF reactions were self-limiting versus reactant exposure. QCM measurements also determined that the mass change per cycle (MCPC) increased with temperature from −4.1 ng/(cm2 cycle) at 150 °C to −18.3 ng/(cm2 cycle) at 250 °C. These MCPC values correspond to etch rates from 0.14 A/cycle at 150 °C to 0.61 A/cycle at 250 °C based on the Al2O3 ALD film density of 3.0 g/cm3. X-ray reflectivity (XRR) analysis confirmed the linear removal of Al2O3 and measur...

Atomic layer etching of Al2O3 using sequential, self-limiting thermal reactions with Sn(acac)2 and hydrogen fluoride.

integrations and challenges of novel high-k gate stacks in advanced cmos technology

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Emerging Applications for High K Materials in VLSI Technology

Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern.

Methods for nanoscale feature imprint molding

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO/sub 2/ gate dielectric. The wet etch of TaSiN had a minimal impact on HfO/sub 2/ (/spl Delta/EOT<1/spl Aring/). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L/sub g/ down to 85nm.

Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

We report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. We demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for V TH control with single high-k and metal gate stack. These attributes taken together constitute a simple non-planar cMOS integration sequence with enhanced drive current for future high performance technology nodes.

Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node

Plasma-based dry etch is used as the industry standard gate etch in conventional CMOS fabrication flow. However, past studies indicate that plasma-induced dry etch may impact device performance. The current research trend toward replacing conventional silicon dioxide and polysilicon gate stacks with high-k/metal gate stacks introduces a new challenge: development of new dry etch processes for critical new metals and their alloys. In this letter, a comparative study in the context of device performance has been conducted to compare dry etch versus wet etch for gate stack etch of hafnium oxide/tantalum silicon nitride gate stack. It has been found that the dry-etched gate stack exhibit significantly more gate leakage current and poorer uniformity in threshold-voltage distribution

Plasma-Induced Damage in High- $k$ /Metal Gate Stack Dry Etch

Using a presilicide implantation approach, we demonstrate that the Schottky barrier height (SBH) of NiSi/n-Si(100) can be modulated by doping a Si substrate with a halogen species such as chlorine. Activation energy measurements indicate that an ultralow barrier of 0.08 eV for NiS/n-Si can be achieved when a high dose (~1 times 1015 cm2) of chlorine is implanted prior to Ni silicidation. A secondary ion mass spectroscopy analysis on the presilicide Cl-implanted NiSi shows chlorine segregates at the interface with SBH tuning from 0.68 to 0.08 eV on n-Si and a corresponding increase in hole SBH on p-Si(100). The presilicide Cl-implanted NiSi film also demonstrates an enhanced thermal stability with a low sheet resistively of < 28 muOmega even up to 850degC.

B. Sassman

Papers

Methods for nanoscale feature imprint molding

Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node

Plasma-Induced Damage in High- $k$ /Metal Gate Stack Dry Etch

Effective Modulation of Ni Silicide Schottky Barrier Height Using Chlorine Ion Implantation and Segregation