J
J.H. Sim
Researcher at SEMATECH
Publications - 33
Citations - 674
J.H. Sim is an academic researcher from SEMATECH. The author has contributed to research in topics: High-κ dielectric & Gate dielectric. The author has an hindex of 15, co-authored 33 publications receiving 648 citations.
Papers
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Journal ArticleDOI
Mechanism of Electron Trapping and Characteristics of Traps in $\hbox{HfO}_{2}$ Gate Stacks
Gennadi Bersuker,J.H. Sim,Chang Seo Park,Chadwin D. Young,S. Nadkarni,Rino Choi,Byoung Hun Lee +6 more
TL;DR: In this paper, the authors proposed a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping).
Proceedings ArticleDOI
Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)
Byoung Hun Lee,Chadwin D. Young,Rino Choi,J.H. Sim,Gennadi Bersuker,C. Y. Kang,R. Harris,George A. Brown,Ken Matthews,Seung-Chul Song,Naim Moumen,Joel Barnett,Patrick S. Lysaght,Kisik Choi,Huang-Chun Wen,Craig Huffman,Husam N. Alshareef,Prashant Majhi,Sundararaman Gopalan,Jeffrey J. Peterson,P. Kirsh,Hong-Jyh Li,J. Gutt,M. Gardner,Howard R. Huff,Peter Zeitzoff,R.W. Murto,L. Larson,C. Ramiller +28 more
TL;DR: In this article, fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability.
Journal ArticleDOI
Validity of constant voltage stress based reliability assessment of high-/spl kappa/ devices
Byoung Hun Lee,Rino Choi,J.H. Sim,Siddarth A. Krishnan,Jeff J. Peterson,George A. Brown,Gennadi Bersuker +6 more
TL;DR: In this paper, the authors review high/spl kappa/ materials specific phenomena that can affect the validity of constant-voltage-stress-based reliability test methods to address the direction of future reliability study on high-/spl Kappa/ devices.
Journal ArticleDOI
Integration of dual metal gate CMOS on high-k dielectrics utilizing a metal wet etch process
Zhibo Zhang,Seung-Chul Song,Craig Huffman,Muhammad Mustafa Hussain,Joel Barnett,Naim Moumen,Husam N. Alshareef,Prashant Majhi,J.H. Sim,S.H. Bae,Byoung Hun Lee +10 more
TL;DR: In this paper, a plasma etch process is developed to etch TaSiN and Ru dual metal gate stacks simultaneously on the same wafer, which can be applied to various metal gate materials.
Proceedings ArticleDOI
High performance gate first HfSiON dielectric satisfying 45nm node requirements
Manuel Quevedo-Lopez,Siddarth A. Krishnan,D. Kirsch,C.H.J. Li,J.H. Sim,Craig Huffman,Jeff J. Peterson,Byoung Hun Lee,G. Pant,B. E. Gnade,M. J. Kim,Robert M. Wallace,D. Guo,H. Bu,Tso-Ping Ma +14 more
TL;DR: In this article, an ALD-based HfSiON gate dielectric scaled to 1 nm EOT with excellent performance and reliability is presented, which can achieve electron and hole mobilities comparable to that of SiON.