Figures of merit connecting processing capabilities with power dissipated (OpS/Watt, Joule/bit, etc.) are becoming dominant factors in choosing technologies for implementing the next generation of computing and communication network systems. Superconductivity is viewed as a technology capable of achieving higher energy efficiencies than other technologies. Static power dissipation of standard RSFQ logic, associated with dc bias resistors, is responsible for most of the circuit power dissipation. In this paper, we review and compare different superconductor digital technology approaches and logic families addressing this problem. We present a novel energy-efficient single flux quantum logic family, ERSFQ/eSFQ. We also discuss energy-efficient approaches for output data interface and overall cryosystem design.

/pdf/energy-efficient-single-flux-quantum-technology-144o6vu2zy.pdf

Energy-Efficient Single Flux Quantum Technology

Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6T) SRAM and proposes an alternative bitcell that functions too much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip.

A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be designed for exceptional stability and write margins, array-level implications must also be considered to achieve a viable memory solution. These constraints can be addressed by modifying traditional 6T-SRAM techniques and conceding some design complexity and area penalties. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies. The proposed 8T solution is demonstrated in a high-performance 32 kb subarray designed in 65 nm PD-SOI CMOS that operates at 5.3 GHz at 1.2 V and 295 MHz at 0.41 V.

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer's foot voltage enable sub-T4 write and read without degrading the bit-cell's density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power.

/pdf/a-256-kb-65-nm-8t-subthreshold-sram-employing-sense-25a3g3pdql.pdf

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

A 4Mb SRAM is designed and fabricated on a 65nm CMOS technology. It features a 0.57 /spl mu/m/sup 2/ 6T cell with large noise margin down to 0.7V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with sleep transistor. It also has a built-in programmable defect "screen" circuit for high volume manufacturing.

SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

Memory with dynamically adjustable supply

A 50 Mb SRAM chip is designed and fabricated on an industry leading 90 nm CMOS technology that features a 1 /spl mu/m/sup 2/ SRAM cell and 50 nm gate length transistors with strained silicon. The SRAM chip is formed with 100/spl times/512 Kb subarrays that have 2.5 GHz nominal operating frequency, 75% area efficiency, and fully synchronized internal timing along with efficient local power-down feature. And the design can be easily re-configured to form large high-density on-die cache memory for high-speed logic applications such as CPUs.

http://ieeexplore.ieee.org/iel5/8656/27435/01221219.pdf

B. Zheng

Papers

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

Memory with dynamically adjustable supply

A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications