K
Kevin Zhang
Researcher at Intel
Publications - 120
Citations - 5514
Kevin Zhang is an academic researcher from Intel. The author has contributed to research in topics: Static random-access memory & CMOS. The author has an hindex of 37, co-authored 120 publications receiving 5299 citations.
Papers
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Proceedings ArticleDOI
A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size
Sanjay Natarajan,M. Agostinelli,S. Akbar,M. Bost,A. Bowonder,V. Chikarmane,S. Chouksey,A. Dasgupta,K. Fischer,Q. Fu,Tahir Ghani,M. Giles,S. Govindaraju,R. Grover,W. Han,D. Hanken,E. Haralson,M. Haran,M. Heckscher,R. Heussner,Pulkit Jain,R. James,R. Jhaveri,I. Jin,Hei Kam,Eric Karl,C. Kenyon,Mark Y. Liu,Y. Luo,R. Mehandru,S. Morarka,L. Neiberg,Paul A. Packan,A. Paliwal,C. Parker,P. Patel,R. Patel,C. Pelto,L. Pipes,P. Plekhanov,M. Prince,S. Rajamani,J. Sandford,Sell Bernhard,Swaminathan Sivakumar,Pete Smith,B. Song,K. Tone,T. Troeger,J. Wiedemer,M. Yang,Kevin Zhang +51 more
TL;DR: In this paper, a 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.
Journal ArticleDOI
Integrated nanoelectronics for the future
TL;DR: Given feature sizes as small as a few nanometres, what will the future hold for integrated electronics?
Journal ArticleDOI
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,D. Murray,N. Vallepalli,Yih Wang,B. Zheng,M. Bohr +8 more
TL;DR: In this article, a column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high performance 65-nm CMOS technology.
Proceedings ArticleDOI
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
P. Bai,C. Auth,Sridhar Balakrishnan,M. Bost,Ruth A. Brain,V. Chikarmane,R. Heussner,Makarem A. Hussein,Jack Hwang,D. Ingerly,R. James,J. Jeong,C. Kenyon,E. Lee,Seung Hwan Lee,Nick Lindert,Mark Y. Liu,Z. Ma,T. Marieb,Anand Portland Murthy,Ramune Nagisetty,Sanjay Natarajan,J. Neirynck,Andrew Ott,C. Parker,J. Sebastian,R. Shaheed,Swaminathan Sivakumar,Joseph M. Steigerwald,S. Tyagi,Cory E. Weber,Bruce Woolery,Yeoh Andrew W,Kevin Zhang,M. Bohr +34 more
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Proceedings ArticleDOI
Characterization of multi-bit soft error events in advanced SRAMs
TL;DR: An exhaustive characterization of multi-bit errors in 90/130 nm SRAMs is presented to support bit interleaving rules that make the impact of multi -bit errors negligible.