Z
Zhanping Chen
Researcher at Intel
Publications - 59
Citations - 2923
Zhanping Chen is an academic researcher from Intel. The author has contributed to research in topics: CMOS & Low-power electronics. The author has an hindex of 23, co-authored 57 publications receiving 2862 citations. Previous affiliations of Zhanping Chen include Purdue University.
Papers
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Proceedings ArticleDOI
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
TL;DR: Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.
Journal ArticleDOI
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,D. Murray,N. Vallepalli,Yih Wang,B. Zheng,M. Bohr +8 more
TL;DR: In this article, a column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high performance 65-nm CMOS technology.
Journal ArticleDOI
Design and optimization of dual-threshold circuits for low-voltage low-power applications
TL;DR: In this paper, the dual-threshold technique is used to reduce leakage power by assigning a high-th threshold voltage to some transistors in noncritical paths, and using low-th thresholds transistor in critical path(s).
Proceedings ArticleDOI
Design and optimization of low voltage high performance dual threshold CMOS circuits
TL;DR: This paper uses dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistor in critical paths in order to achieve the best leakage power saving under target performance constraints.
Proceedings ArticleDOI
Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors
TL;DR: An implicit-pulsed, semidynamic flip-flop (ip-DCO) is presented which has the fastest delay of any flip- flop considered, along with a large amount of negative setup time, however, an explicit- pulsed static flip-Flop (ep-SFF) is the most energy-efficient and is ideal for the majority of critical paths in the design.