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Bernabe Linares-Barranco
Researcher at Spanish National Research Council
Publications - 280
Citations - 10991
Bernabe Linares-Barranco is an academic researcher from Spanish National Research Council. The author has contributed to research in topics: Neuromorphic engineering & CMOS. The author has an hindex of 46, co-authored 257 publications receiving 9125 citations. Previous affiliations of Bernabe Linares-Barranco include Texas A&M University & University of Seville.
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Journal ArticleDOI
Hardware Implementation of Deep Network Accelerators Towards Healthcare and Biomedical Applications
Mostafa Rahimi Azghadi,Corey Lammie,Jason K. Eshraghian,Melika Payvand,Elisa Donati,Bernabe Linares-Barranco,Giacomo Indiveri +6 more
TL;DR: In this article, the authors provide a tutorial describing how various technologies including emerging memristive devices, Field Programmable Gate Arrays (FPGAs), and Complementary Metal Oxide Semiconductor (CMOS) can be used to develop efficient DL accelerators to solve a wide variety of diagnostic, pattern recognition, and signal processing problems in healthcare.
Journal ArticleDOI
A CMOS analog adaptive BAM with on-chip learning and weight refreshing
TL;DR: The transconductance-mode (T-mode) approach is extended to implement analog continuous-time neural network hardware systems to include on-chip Hebbian learning and on- chip analog weight storage capability.
On Real-Time AER 2-D Convolutions Hardware for
R. Serrano-Gotarredona,Teresa Serrano-Gotarredona,A.J. Acosta-Jimenez,Clara Serrano-Gotarredona,Jose A. Pérez-Carrasco,Bernabe Linares-Barranco,Alejandro Linares-Barranco,Gabriel Jimenez-Moreno,Antón Civit-Ballcels +8 more
TL;DR: In this article, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is pre-sented, which is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques.
Journal ArticleDOI
On algorithmic rate-coded AER generation
TL;DR: This paper addresses the problem of converting a conventional video stream based on sequences of frames into the spike event-based representation known as the address-event-representation (AER), and finds that simple and straightforward algorithms tend to have high potential for real time but produce event distributions that differ considerably from those obtained in AER VLSI chips.
Journal ArticleDOI
CMOS OTA-C high-frequency sinusoidal oscillators
TL;DR: In this article, several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance amplifier-capacitor (OTA-C) techniques.