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Bernabe Linares-Barranco
Researcher at Spanish National Research Council
Publications - 280
Citations - 10991
Bernabe Linares-Barranco is an academic researcher from Spanish National Research Council. The author has contributed to research in topics: Neuromorphic engineering & CMOS. The author has an hindex of 46, co-authored 257 publications receiving 9125 citations. Previous affiliations of Bernabe Linares-Barranco include Texas A&M University & University of Seville.
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MemTorch: An Open-source Simulation Framework for Memristive Deep Learning Systems.
TL;DR: This paper presents a framework, entitled MemTorch, which adopts a modernized software engineering methodology and integrates directly with the well-known PyTorch Machine Learning (ML) library, and uses it to perform novel simulations of memristive DL systems, which are trained and benchmarked using the CIFAR-10 dataset.
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A real-time clustering microchip neural engine
TL;DR: The clustering algorithm is based on the popular ART1 algorithm, but has been modified resulting in a more VLSI-friendly algorithm that allows a more efficient hardware implementation with simple circuit operators, little memory requirements, modular chip assembly capability, and higher speed figures.
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A new five-parameter MOS transistor mismatch model
TL;DR: In this paper, a new five-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation regions, including short-channel transistors.
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On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems
Amirreza Yousefzadeh,Miroslaw Jablonski,Taras Iakymchuk,Alejandro Linares-Barranco,A. Rosado,Luis A. Plana,Steve Temple,Teresa Serrano-Gotarredona,Steve Furber,Bernabe Linares-Barranco +9 more
TL;DR: This paper presents a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction to transmit 32-bit address events reliably over multiplexed serial connections.
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A programmable neural oscillator cell
TL;DR: In this paper, a programmable analog neural oscillator cell architecture is presented, which consists of two OTAs, a current mirror, a capacitor, a diode, and a resistor.