Bishop Brock

TL;DR: In this paper, a PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described.

TL;DR: An overview of a wide array of new features in the processor and system designs that advance IBM's EnergyScale™ dynamic power management methodology, which include better sensing, more advanced power controls, improved scalability for power management, and features to address the diverse needs of the full range of POWER servers from blades to supercomputers are provided.

TL;DR: During better-than-worst case conditions the guardband management mechanism reduces the average voltage setting 137–152 mV below nominal, resulting in average processor power reduction of 24% with no performance loss while running industry-standard benchmarks.

TL;DR: This work proved the correctness of the kernel of the floating-point division operation on AMD's first Pentium-class microprocessor, the AMD5 K 86, and discussed ACL2 and industrial applications, with particular attention to the microcode verification work.

TL;DR: This paper discusses several of the SOC design issues pertaining to dynamic voltage and frequency scalable systems, and how these issues were resolved in the IBM PowerPC 405LP processor, and introduces DPM, a novel architecture for policy-guided dynamic power management.