Graphene’s success has shown that it is possible to create stable, single and few-atom-thick layers of van der Waals materials, and also that these materials can exhibit fascinating and technologically useful properties. Here we review the state-of-the-art of 2D materials beyond graphene. Initially, we will outline the different chemical classes of 2D materials and discuss the various strategies to prepare single-layer, few-layer, and multilayer assembly materials in solution, on substrates, and on the wafer scale. Additionally, we present an experimental guide for identifying and characterizing single-layer-thick materials, as well as outlining emerging techniques that yield both local and global information. We describe the differences that occur in the electronic structure between the bulk and the single layer and discuss various methods of tuning their electronic properties by manipulating the surface. Finally, we highlight the properties and advantages of single-, few-, and many-layer 2D materials in...

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Progress, Challenges, and Opportunities in Two-Dimensional Materials Beyond Graphene

We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.

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Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises from the repeated capacitance charge and discharge on the output of the hundreds of millions of gates in today's chips. Until recently, only dynamic power has been a significant source of power consumption, and Moore's law helped control it. However, power consumption has now become a primary microprocessor design constraint; one that researchers in both industry and academia will struggle to overcome in the next few years. Microprocessor design has traditionally focused on dynamic power consumption as a limiting factor in system integration. As feature sizes shrink below 0.1 micron, static power is posing new low-power design challenges.

Leakage current: Moore's law meets static power

https://cyberleninka.org/article/n/323323.pdf

Production and processing of graphene and 2d crystals

One-dimensional carbon nanotubes and two-dimensional graphene nanosheets with unique electrical, mechanical and thermal properties are attractive reinforcements for fabricating light weight, high strength and high performance metal-matrix composites. Rapid advances of nanotechnology in recent years enable the development of advanced metal matrix nanocomposites for structural engineering and functional device applications. This review focuses on the recent development in the synthesis, property characterization and application of aluminum, magnesium, and transition metal-based composites reinforced with carbon nanotubes and graphene nanosheets. These include processing strategies of carbonaceous nanomaterials and their composites, mechanical and tribological responses, corrosion, electrical and thermal properties as well as hydrogen storage and electrocatalytic behaviors. The effects of nanomaterial dispersion in the metal matrix and the formation of interfacial precipitates on these properties are also addressed. Particular attention is paid to the fundamentals and the structure–property relationships of such novel nanocomposites.

Recent progress in the development and properties of novel metal matrix nanocomposites reinforced with carbon nanotubes and graphene nanosheets

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

A distributed critical-path timing monitor (CPM) is designed as part of the POWER6trade microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process variation, localized noise and VDD droop, or clock stability. It tracks critical-path delay to within 3 FO2 delays at extreme operating voltages with a standard deviation less than frac12 an FO2 delay. The CPM detects DC VDD droops greater than 10mV and tracks timing changes greater than 1 FO2 delay.

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

Owing in part to scaling challenges for metal oxide semiconductor field-effect transistors (MOSFETs) and complementary metal oxide semiconductor (CMOS) logic, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide improved MOSFET performance beyond the 22 nm node, or provide novel functionality for, e.g. 'beyond CMOS' devices. Graphene, with its novel and electron–hole symmetric band structure and its high carrier mobilities and thermal velocities, is one such material that has garnered a great deal of interest for both purposes. Single and few layer carbon sheets have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapour deposition, and field-effect transistors have been demonstrated with room-temperature mobilities as high as 10 000 cm2 V−1 s−1. But graphene is a gapless semiconductor and gate control of current is challenging, off-state leakage currents are high, and current does not readily saturate with drain voltage. However, various ways to overcome, adapt to, or even embrace this property are now being considered for device applications. In this work we explore through illustrative examples the potential of and challenges to graphene use for conventional and novel device applications.

https://iopscience.iop.org/article/10.1088/0022-3727/44/31/313001/pdf

Graphene field-effect transistors

We demonstrate the synthesis of large-area graphene on Co, a complementary metal-oxide-semiconductor (CMOS)-compatible metal, using acetylene (C2H2) as a precursor in a chemical vapor deposition (CVD)-based method. Cobalt films were deposited on SiO2/Si, and the influence of Co film thickness on monolayer graphene growth was studied, based on the solubility of C in Co. The surface area coverage of monolayer graphene was observed to increase with decreasing Co film thickness. A thorough Raman spectroscopic analysis reveals that graphene films, grown on an optimized Co film thickness, are principally composed of monolayer graphene. Transport properties of monolayer graphene films were investigated by fabrication of back-gated graphene field-effect transistors (GFETs), which exhibited high hole and electron mobility of ∼1600 cm2/V s and ∼1000 cm2/V s, respectively, and a low trap density of ∼1.2 × 1011 cm–2.

CMOS-compatible synthesis of large-area, high-mobility graphene by chemical vapor deposition of acetylene on cobalt thin films

Recently, graphene field-effect transistors (FET) with cutoff frequencies (fT) between 100 and 300 GHz have been reported; however, the devices showed very weak drain current saturation, leading to an undesirably high output conductance (gds= dIds/dVds). A crucial figure-of-merit for analog/RF transistors is the intrinsic voltage gain (gm/gds) which requires both high gm (primary component of fT) and low gds. Obtaining current saturation has become one of the key challenges in graphene device design. In this work, we study theoretically the influence of the dielectric thickness on the output characteristics of graphene FETs by using a surface-potential-based device model. We also experimentally demonstrate that by employing a very thin gate dielectric (equivalent oxide thickness less than 2 nm), full drain current saturation can be obtained for large-scale chemical vapor deposition graphene FETs with short channels. In addition to showing intrinsic voltage gain (as high as 34) that is comparable to commer...

Gary D. Carpenter

Papers

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

Graphene field-effect transistors

CMOS-compatible synthesis of large-area, high-mobility graphene by chemical vapor deposition of acetylene on cobalt thin films

Current saturation in submicrometer graphene transistors with thin gate dielectric: experiment, simulation, and theory.