Christopher J. Berry

TL;DR: The next-generation System z design introduces a new microprocessor chip (CP) and a system controller chip (SC) aimed at providing a substantial boost to maximum system capacity and performance compared to the previous zEC12 design in 32nm.

TL;DR: In this paper, the receiving chip separately latches each half of the data received from the double data rate bus, each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal Chip cycle time.

TL;DR: In this paper, the authors propose a method for data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances.

TL;DR: The IBM Z microprocessor in the z14 system has been redesigned to improve performance, system capacity, and security over the previous z13 system, and is designed in Global Foundries 14nm high performance SOI FinFET technology with 17 layers of copper interconnect.

TL;DR: In this paper, a design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks is described in terms of reducing and balancing the load inside each clock sector, although the techniques may also be applied to balancing load between clock sectors.