An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

3D semiconductor device and structure

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

In this brief, a novel U-shape-channel tunneling field-effect transistor (UTFET) with a SiGe source region is investigated by 2-D technology computer aided design simulation. The enlarged tunneling area and enhanced tunneling rate dramatically increase the tunneling current when the device is turned on. Meanwhile, the off-leakage current of UTFET is suppressed because of the extended physical channel length. The on-state tunneling current of UTFET can be further improved by introducing an n+-doped Si delta layer under the source region. The inserted delta layer significantly shortens the band-to-band tunneling path, enlarges tunneling area, and thus enhances the tunneling rate of this device. The average value of the subthreshold swing (SS) of the optimized UTFET is 58 mV/dec when VGS is varied from 0 to 0.46 V. Using the SiGe-source UTFET structure with a delta layer, the merits of low leakage current, high drive current, and ultralow SS can be realized simultaneously.

Design of U-Shape Channel Tunnel FETs With SiGe Source Regions

This paper presents a 2-D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2-D Poisson's equation. From the potential profile, the electric field is derived and then the drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the tunneling region. The model well predicts the potential, subthreshold swing (SS), and transfer and output characteristics of DG TFETs. We analyze the dependence of the tunneling current on the device parameters by varying the gate oxide dielectric constant, gate oxide thickness, body thickness, channel length and channel material and also demonstrate its agreement with TCAD simulation results. The SS which describes the switching behavior of TFETs, is derived from the current expression. The comparisons show that the SS of our model well coincides with that of simulations.

/pdf/a-2-d-analytical-model-for-double-gate-tunnel-fets-4qfa6mrfwc.pdf

A 2-D Analytical Model for Double-Gate Tunnel FETs

We demonstrate tunable Schottky barrier height and record photo-responsivity in a new-concept device made of a single-layer CVD graphene transferred onto a matrix of nanotips patterned on n-type Si wafer. The original layout, where nano-sized graphene/Si heterojunctions alternate to graphene areas exposed to the electric field of the Si substrate, which acts both as diode cathode and transistor gate, results in a two-terminal barristor with single-bias control of the Schottky barrier. The nanotip patterning favors light absorption, and the enhancement of the electric field at the tip apex improves photo-charge separation and enables internal gain by impact ionization. These features render the device a photodetector with responsivity (3 A/W for white LED light at 3 mW/cm2 intensity) almost an order of magnitude higher than commercial photodiodes. We extensively characterize the voltage and the temperature dependence of the device parameters and prove that the multi-junction approach does not add extra-inhomogeneity to the Schottky barrier height distribution. This work represents a significant advance in the realization of graphene/Si Schottky devices for optoelectronic applications.

https://iopscience.iop.org/article/10.1088/2053-1583/4/1/015024/pdf

Tunable Schottky barrier and high responsivity in graphene/Si-nanotip optoelectronic device

This study presents a new sub-10-nm tunnel field-effect transistor (TFET) with bandgap engineering using a graded Si/Ge heterojunction. Both the height and width of the tunneling barrier are highly controlled by applying gate voltages to ensure a near ideal sub-5-mV/dec switching of scaled sub-10-nm TFETs at 300 K. This study performed a 2-D simulation to elucidate p-body graded Si/Ge heterojunction TFET devices from 50 to 5 nm. The on-state tunneling barrier around the source was narrowed and lowered to demonstrate a high on-current; simultaneously, the off-state tunneling barrier was raised and extended into the drain to control the short-channel effect and ambipolar leakage current. The shorter the length is, the more abrupt is the switching. The breakthrough in subthreshold swing and short-channel effect make the graded Si/Ge TFET highly promising as an ideal green transistor into sub-10-nm regimes.

Sub-10-nm Tunnel Field-Effect Transistor With Graded Si/Ge Heterojunction

Using graded silicon-germanium heterojunctions, the green tunnel field-effect transistor (TFET) can be scaled down into sub-10 nm regimes without short-channel effects. This work elucidates numerically the physical operation and device design of extremely short-channel TFETs with graded silicon-germanium heterojunctions for future low-power and high-performance applications. Critical device factors, such as the drain profile and bandgap engineering, were examined to generate favorable characteristics in the on-current, on-off switching, and off-leakage of very short TFETs. A mildly doped drain with a pure Ge source is preferred in designing the graded TFETs to optimize a desirable green transistor for low-power integrated circuits.

Physical operation and device design of short-channel tunnel field-effect transistors with graded silicon-germanium heterojunctions

The low-bandgap engineering and line-tunneling architecture are the two major techniques to resolve the ON-current issues of tunnel field-effect transistors (TFETs). This paper elucidates the design and modeling of line-tunneling TFETs using low-bandgap materials. Three semiconductors, Ge, InAs, and InSb, are considered as examples to explore their physical operations and analytical models. 2-D device simulations were performed to examine the on/off characteristics. The appropriate operational voltages depend on the associated bandgap of semiconductors. The gate voltage should be larger than the bandgap voltage $(E_{g}/q)$ to ensure high ON-currents, whereas the drain voltage must be less than the bandgap voltage to control OFF-leakages. Because the minimum tunnel path has a key function in determining the tunneling in line-tunneling TFETs, the tunneling current is reformulated in terms of the minimum tunnel path with friendly compact forms. Two prime design factors, the source concentration and gate-insulator thickness, are examined both analytically and numerically, showing the minimum tunnel path can serve as a useful indicator for low-bandgap line-tunneling TFETs.

Design and Modeling of Line-Tunneling Field-Effect Transistors Using Low-Bandgap Semiconductors

This paper presents a novel Schottky barrier multibit cell with source-side injected programming and reverse drain-side hole erasing. Based on the unique ambipolar conduction of Schottky barrier devices, the source Schottky barrier promotes the amounts of hot electrons at a positive gate voltage to perform source-side injected programming, whereas the drain Schottky barrier enhances the generations of hot holes at a negative gate voltage to carry out reverse drain-side erasing. The proposed Schottky barrier charge-trapping cells are numerically demonstrated to exhibit low-voltage and high-efficiency programming/erasing without the presence of any gate versus source/drain bias tradeoff. The tight and matched distributions of injected carriers make this Schottky barrier cell excellent in future multibit-cell applications.

Nonvolatile Schottky Barrier Multibit Cell With Source-Side Injected Programming and Reverse Drain-Side Hole Erasing

A novel multilevel Schottky barrier nonvolatile nanowire memory is experimentally reported with low-voltage operations and excellent reliability. Using efficient hot-electrons and hot-holes generation associated with Schottky barrier source/drain, the multilevel schemes of silicon nanowire silicon-oxide-nitride-oxide-silicon (SONOS) cells are achieved at adequately low gate voltages. The n-channel cells work at a small gate voltage of 5 to 7 V using multilevel electron programming, whereas the p-channel cells operate at a low gate voltage of -7 to -11 V using multilevel hole programming. The roles of electron and hole carriers in the n-channel cells are exchanged in the p-channel nanowire cells because of ambipolar conduction. Both the n- and p-channel multilevel Schottky barrier nanowire SONOS cells preserve excellent thermal retention and cycling endurance for use in practical embedded and stand-alone nonvolatile memories.

Chun-Hsing Shih

Papers

Sub-10-nm Tunnel Field-Effect Transistor With Graded Si/Ge Heterojunction

Physical operation and device design of short-channel tunnel field-effect transistors with graded silicon-germanium heterojunctions

Design and Modeling of Line-Tunneling Field-Effect Transistors Using Low-Bandgap Semiconductors

Nonvolatile Schottky Barrier Multibit Cell With Source-Side Injected Programming and Reverse Drain-Side Hole Erasing

Multilevel Schottky Barrier Nanowire SONOS Memory With Ambipolar n- and p-Channel Cells