The performance of electronic and optoelectronic devices based on two-dimensional layered crystals, including graphene, semiconductors of the transition metal dichalcogenide family such as molybdenum disulphide (MoS2) and tungsten diselenide (WSe2), as well as other emerging two-dimensional semiconductors such as atomically thin black phosphorus, is significantly affected by the electrical contacts that connect these materials with external circuitry. Here, we present a comprehensive treatment of the physics of such interfaces at the contact region and discuss recent progress towards realizing optimal contacts for two-dimensional materials. We also discuss the requirements that must be fulfilled to realize efficient spin injection in transition metal dichalcogenides.

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Electrical contacts to two-dimensional semiconductors

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.

Hot-electron-induced MOSFET degradation&#8212;Model, monitor, and improvement

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with a physical model involving the breaking of the = Si/sub s/H bonds. The device lifetime /spl tau/ is proportional to...

Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement

In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions and applied voltages, while still maintaining constant the shape of the electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increase. The resulting design flexibility allows the design of FET's with quarter-micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scaling theory are then investigated in detail, leading to the conclusion that the limiting FET performances are not reached at the 0.25-µm channel length. Further improvements are possible in the future, provided certain technology breakthroughs are achieved.

Generalized scaling theory and its application to a &#188; micrometer MOSFET design

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi 2 , and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.

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Optimal interconnection circuits for VLSI

In scaled technologies, performance improvements become increasingly limited by interconnect parasitics. The increased emphasis in the literature on low-resistance replacements for, or supplements to, polysilicon-gate technologies verifies the importance of parasitic limitations. Further, the role of the series source and drain resistance as well as contact resistance in limiting device performance has also been addressed by several authors. This role is further enhanced by the actual much more rapid increase in sheet resistivity with decreasing junction depth than previously assumed by other workers. In fact, it can be anticipated that metallurgical advances, such as silicides, will be required to compensate for the increased sheet resistance of source and drain diffusions. In the present work, a theoretical development of a transmission line model for a totally silicided diffusion is presented. Both the silicide and the diffusion sheet resistivities ρ S and ρ D , and the specific contact resistivity ρ c , are incorporated, unlike earlier models for contact holes only in which ρ S = 0. This model is applied to specific typical MOS structures, including single-section and three-section structures, to calculate the contact resistance contribution to total resistance. These results are used in conjunction with device equations addressing the device and circuit performance of small-geometry MOSFET's. Both n- and p-channel devices are considered as well as various scaling scenarios (constant field, constant voltage, etc.). These results show that for n-channel devices with a gate length of 1 µm, a-factor-of-two increase in circuit performance can be expected when using silicides. However, for p-channel devices, the expected performance gain as a result of using silicides is a factor of ten.

A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits

The high drain-effect transistor characteristic observed after hot-carrier injection and trapping in the oxide has been found to be due to the uneven trapped-carrier distribution near the drain, which causes the threshold voltage to vary as a function of drain voltage. A discussion of the role and effects of both electron and hole injection is presented. The nonlinear distribution of carriers trapped in the gate oxide is described. One result is that the nonuniform surface band bending causes the subthreshold leakage to be an exponential function of the drain voltage. The combined increase in threshold voltage, subthreshold leakage, and a decrease in subthreshold slope will translate into slower circuit speed and higher standby power dissipation [37] in CMOS circuits. An experimental model of the mean time to failure, for NMOS devices fabricated with two different source-drain diffusions, is also presented. For the first time, the model has been extended to include the channel-length dependence. The model assumes a reliability criterion of less than a 10-mV threshold-voltage shift in 100 000 h of operation. Experimental results and subsequent calculations show that for 350-A gate-oxide devices at 5.0 V operation, 2.5 µm is the minimum electrical channel-length device which can be fabricated using a traditional source-drain process. Conversely, submicrometer electrical channel-length devices can be fabricated using an arsenic-phosphorous "graded" source-drain process, even at 5.5-V operation.

Reliability effects on MOS transistors due to hot-carrier injection

The high drain-effect transistor characteristic observed after hot-carrier injection and trapping in the oxide has been found to be due to the uneven trapped-carrier distribution near the drain, which causes the threshold voltage to vary as a function of drain voltage. A discussion of the role and effects of both electron and hole injection is presented. The nonlinear distribution of carriers trapped in the gate oxide is described. One result is that the nonuniform surface band bending causes the subthreshold leakage to be an exponential function of the drain voltage. The combined increase in threshold voltage, subthreshold leakage, and a decrease in subthreshold slope will translate into slower circuit speed and higher standby power dissipation [37] in CMOS circuits. An experimental model of the mean time to failure, for NMOS devices fabricated with two different source-drain diffusions, is also presented. For the first time, the model has been extended to include the channel-length dependence. The model assumes a reliability criterion of less than a 10-mV threshold-voltage shift in 100 000 h of operation. Experimental results and subsequent calculations show that for 350-/spl Aring/ gate-oxide devices at 5.0 V operation, 2.5 /spl mu/m is the minimum electrical channel-length device which can be fabricated using a traditional source-drain process. Conversely, submicrometer electrical channel-length devices can be fabricated using an arsenic-phosphorous "graded" source-drain process, even at 5.5-V operation.

Reliability Effects on MOS Transistors Due to Hot-Carrier Injection

In sealed technologies, performance improvements become increasingly tilted by interconnect parasitic. The increased emphasis in the literature on low-resistance replacements for, or supplements to, polysilicon-gate technologies verifies the importance of parasitic limitations. Further, the role of the series source and drain resistance as well as contact resistance in limiting device performance has also been addressed by several authors. This role is further enhanced by the actual much more rapid increase in sheet resistivity with decreasing junction depth than previously assumed by other workers. In fact, it can be anticipated that metallurgical advances, such as silicides, will be required to compensate for the increased sheet resistance of source and drain diffusions. In the present work, a theoretical development of a transmission line model for a totally silicided diffusion is presented. Both the silicide and the diffusion sheet resistivities/spl rho//sub S/ and /spl rho//sub D/, and the specific contact resistivity /spl rho//sub c/, are incorporated, unlike earlier models for contact holes only in which /spl rho//sub S/ =0. This model is applied to specific typical MOS structures, including single-section and three-section structures, to calculate the contact resistance contribution to total resistance. These results are used in conjunction with device equations addressing the device and circuit performance of small-geometry MOSFET's. Both n- and p-channel devices are considered as well as various scaling scenarios (constant field, constant voltage, etc.). These results show that for n-channel devices with a gate length of 1 /spl mu/m, a-factor-of two increase in circuit performance can be expected when using silicides. However, for p-channel devices, the expected performance gain as a result of using silicides is a factor of ten.

D.B. Scott

Papers

A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits

Reliability effects on MOS transistors due to hot-carrier injection

Reliability Effects on MOS Transistors Due to Hot-Carrier Injection

A Transmission Line Model for Silicided Diffusions: Impact on the Performance of VLSI Circuits

A New Transmission Line Model for Silicided Diffusions: Impact on the Performance of VLSI Circuits