A monolithic 1.9-GHz, 198-mW, 0.6-/spl mu/m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF with double conversion architecture which eliminates the need for the discrete-component noise and IF filters in addition to facilitating the eventual integration of the frequency synthesizer blocks with on-chip VCO's. The prototype device utilizes a 3.3-V supply and includes a low noise amplifier, an image-rejection mixer, and two quadrature baseband signal paths each of which includes a second-order Sallen and Key anti-alias filter, an eighth-order switched-capacitor filter network followed by a 10-b pipelined analog-to-digital converter (ADC). The experimental device has a measured receiver reference sensitivity of -90 dBm, an input referred IP3 of -7 dBm, a P/sub -1 dB/ of -24 dBm, and an image-rejection ratio of -55 dBc across the DECT bands.

A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications

This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

/pdf/low-power-low-phase-noise-differentially-tuned-quadrature-q31y9qihqr.pdf

Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-/spl mu/m CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement.

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MOS transistor modeling for RF IC design

This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels.

Noise optimization of an inductively degenerated CMOS low noise amplifier

A noise analysis of current-commutating CMOS mixers, such as the widely used CMOS Gilbert cell, is presented. The contribution of all internal and external noise sources to the output noise is calculated. As a result, the noise figure can be rapidly estimated by computing only a few parameters or by reading them from provided normalized graphs. Simple explicit formulas for the noise introduced by a switching pair are derived, and the upper frequency limit of validity of the analysis is examined. Although capacitive effects are neglected, the results are applicable up to the gigahertz frequency range for modern submicrometer CMOS technologies. The deviation of the device characteristics from the ideal square law is taken into account, and the analysis is verified with measurements.

/pdf/noise-in-current-commutating-cmos-mixers-3ykuegk729.pdf

Noise in current-commutating CMOS mixers

An analytical formulation of the thermal noise in short-channel MOSFETs, working in the saturation region, is presented. For the noise calculation, we took into account effects like the field dependent noise temperature and mobility, the device geometry and the channel length modulation, the back gate effect and the velocity saturation. The derived data from the model are in good agreement with reported thermal noise measurements, regarding the noise bias dependence, for transistors with channel lengths shorter than 1 /spl mu/m. Since the present thermal noise models of MOS transistors are valid for channel lengths well above 1 /spl mu/m, the proposed model can be easily incorporated in circuit simulators like SPICE, providing an extension to the analytical thermal noise modeling suitable for submicron MOSFETs.

Thermal noise modeling for short-channel MOSFETs

At high frequencies the gate admittance of the MOSFET contains a conductive component because of the capacitive coupling of the gate electrode to the channel. The thermal noise fluctuations, originating in the channel, induce a gate current outwards from the gate electrode. Based on a proved two-region model for the drain current noise of a sub-micron MOSFET, it is shown that the calculated gate-noise current increases significantly, compared to that predicted by a classical model, valid for long channel devices.

Induced gate noise in MOSFETs revisited: The submicron case

The wide band noise voltage (equivalent thermal noise voltage at the gate) of a submicron MOSFET, working in saturation, exhibits a minimum value at a certain drain current. This is supported by measurements and theoretical analysis based on a suitable thermal noise model. This macroscopic noise model attributes the thermal noise of the drain current to the superposition of two noise sources originating from two separate regions of the transistor's channel (a gradual channel approximation region and a saturation region). The existence of a minimum of the noise spectral density at an optimum drain current (I/sub opt/), is well proved by measurements and is contradictory to the predictions of the current simulation program with integrated circuit emphasis (SPICE) models. An empirical way for evaluating analytically I/sub opt/ is given. The fact of the existence of a noise minimum for a submicron MOSFET, brings a phenomenological equivalence to the bipolar transistor and GaAs MESFET when they are employed at the first stage of an amplifier.

Optimal current for minimum thermal noise operation of submicrometer MOS transistors

In optical (charge) amplifier design, it is common practice, to size the input MOSFET so that the amplifier's input capacitance is approximately equal to the value of the photodiode capacitance. When plotted versus capacitance, the input equivalent noise current reaches its minimum value, for a given drain bias current, in a curve widely known and characterized as a shallow one. For high bit rate photocurrent amplifiers, which employ short-channel MOSFET's as the input device, the observed sensitivity degradation is due to the increased input referred noise attributed to the MOSFET's short-channel operation. It is shown here that for short-channel MOSFET's the electron warming in the channel, the voltage fluctuations due to the gate polysilicon resistance, and the induced thermal noise at the gate, lead to a considerably lower value for the optimum input capacitance. In this case, the noise power versus the capacitance curve becomes steeper and the minimum is more prominent.

Input capacitance scaling related to short-channel noise phenomena in MOSFET's

The authors deal with the implementation of a monolithic optical amplifier for SDH/SONET applications operating at speeds up to 622 Mbit/s. The amplifier incorporates automatic gain control (AGC) and differential output, so it is capable of being connected directly to a quantiser and a clock recovery chip-set. The presented design is fabricated on a cheap 1.2 /spl mu/m BiCMOS technology which is actually an enhanced CMOS technology offering only NPN bipolar transistors.

http://ieeexplore.ieee.org/iel5/2190/16993/00785295.pdf

D.P. Triantis

Papers

Thermal noise modeling for short-channel MOSFETs

Induced gate noise in MOSFETs revisited: The submicron case

Optimal current for minimum thermal noise operation of submicrometer MOS transistors

Input capacitance scaling related to short-channel noise phenomena in MOSFET's

Monolithic amplifier with AGC and differential output for 622 Mbit/s optical communications