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Journal ArticleDOI

Thermal noise modeling for short-channel MOSFETs

D.P. Triantis, +2 more
- 01 Nov 1996 - 
- Vol. 43, Iss: 11, pp 1950-1955
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TLDR
In this article, an analytical formulation of the thermal noise in short-channel MOSFETs, working in the saturation region, is presented, taking into account effects like the field dependent noise temperature and mobility, the device geometry and the channel length modulation, the back gate effect and the velocity saturation.
Abstract
An analytical formulation of the thermal noise in short-channel MOSFETs, working in the saturation region, is presented. For the noise calculation, we took into account effects like the field dependent noise temperature and mobility, the device geometry and the channel length modulation, the back gate effect and the velocity saturation. The derived data from the model are in good agreement with reported thermal noise measurements, regarding the noise bias dependence, for transistors with channel lengths shorter than 1 /spl mu/m. Since the present thermal noise models of MOS transistors are valid for channel lengths well above 1 /spl mu/m, the proposed model can be easily incorporated in circuit simulators like SPICE, providing an extension to the analytical thermal noise modeling suitable for submicron MOSFETs.

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A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications

TL;DR: A description is given of a wide-band IF with double conversion architecture which eliminates the need for the discrete-component noise and IF filters in addition to facilitating the eventual integration of the frequency synthesizer blocks with on-chip VCO's.
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Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

TL;DR: A novel fully differential frequency tuning concept is introduced to ease high integration of VCOs with quadrature outputs and leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption.
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MOS transistor modeling for RF IC design

TL;DR: In this article, the authors present the basis of the modeling of the MOS transistor for circuit simulation at RF and present a physical equivalent circuit that can be easily implemented as a Spice subcircuit.
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Noise optimization of an inductively degenerated CMOS low noise amplifier

TL;DR: The total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA, and very low noise figures become possible already at very low power consumption levels.
Journal ArticleDOI

Noise in current-commutating CMOS mixers

TL;DR: In this paper, a noise analysis of current-commutating CMOS mixers, such as the widely used CMOS Gilbert cell, is presented, where the contribution of all internal and external noise sources to the output noise is calculated.
References
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Book

Noise in solid state devices and circuits

TL;DR: In this paper, the authors propose a method to generate 1/f noise noise in particular Amplifier Circuits Mixers by using thermal noise shot and flicker noise, respectively.
Journal ArticleDOI

High-frequency noise measurements on FET's with small dimensions

TL;DR: In this article, a low-noise high-frequency transresistance amplifier was used to accurately measure broadband noise in MOSFETs with small widths and submicrometer channel lengths.
Journal ArticleDOI

A simple two-dimensional model for IGFET operation in the saturation region

TL;DR: In this paper, a model for an IGFET operating in saturation and accounting for the two-dimensional potential distribution in the section of the surface space-charge region adjacent to the drain is developed.
Journal ArticleDOI

An engineering model for short-channel MOS devices

TL;DR: An engineering model for short-channel MOS devices which includes the effect of carrier drift velocity saturation is described in this article, where simplified expressions for the DC drain current I/sub D/, the small signal transconductance g/sub m/ and the output conductance G/sub ds/ in the saturation region are derived.
Journal ArticleDOI

MOSFET thermal noise modeling for analog integrated circuits

TL;DR: In this article, the effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated, and a model that is capable of predicting the thermal noises of both long and short channel devices in both the triode and saturation regions is presented.