A recently developed computational imaging technique, X-ray ptychographic tomography, is used to study integrated circuits, and a 3D image of a processor chip with a resolution of 14.6 nm is obtained. As computer chips have become increasingly crammed with nanometre-scale devices and circuitry, new microscopy techniques that can resolve the smallest features are required to enable chip design and inspection. X-ray imaging is uniquely suited for non-destructive, high-resolution imaging and Mirko Holler et al. make use of a recently developed computational imaging technique, X-ray ptychography, to generate high-resolution three-dimensional images of integrated circuits. They test X-ray ptychography on a circuit with known features, and then apply it to an Intel processor chip manufactured in the 22-nanometre technology, obtaining detailed three-dimensional maps of the devices with a resolution down to 14.6 nanometres. This technique could be used to assist quality control during chip production. Modern nanoelectronics1,2 has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography3,4—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques5,6,7. Foreseeable developments in X-ray sources8, optics9 and detectors10, as well as adoption of an instrument geometry11 optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

High-resolution non-destructive three-dimensional imaging of integrated circuits

In this letter, we show that Giant Spin Hall Effect (GSHE) MRAM can enable better energy- delay and voltage performance than traditional MTJ based spin torque devices at scaled nanomagnet dimensions (10-30 nm). Firstly, we derive the effect of dimensional scaling on spin injection efficiency, voltage-delay and energy-delay of spin torque switching using MTJs and GSHE and identify the optimum electrode geometry for low operating voltage ( 10 GHz) operation. We show that effective spin injection efficiency >100 % can be obtained using optimum spin hall electrode thickness for 30 nm nanomagnet widths. Finally, we derive the energy-delay trajectory of GSHE and MTJ devices to calculate the energy-delay product of GSHE and MTJ devices with an energy minimum at the characteristic time of the magnets. Optimized GSHE devices when combined with PMA can enable MRAM with scaled nanomagnets (30 nm X 60 nm), ultra-low voltage operation (< 0.1 V), fast switching times (10 ps) and switching energy as low as 100 aJ/bit.

Voltage and Energy-Delay Performance of Giant Spin Hall Effect Switching for Magnetic Memory and Logic

We show that the giant spin Hall effect (GSHE) magnetoresistive random access memory (MRAM) can enable better energy delay and voltage performance than MTJ spin torque devices at 10?30 nm scaled nanomagnet dimensions. We propose a dense bit cell composed of a folded electrode to enable scaling to sub-10 nm CMOS. We derive the energy-delay trajectory and energy-delay product of GSHE and MTJ devices with an energy minimum at the magnetic characteristic time. Optimized GSHE devices with PMA can enable low voltage (<0.1 V), scaled dimensions, and fast switching time (100 ps) at an average switching energy approaching 100 aJ/bit.

http://iopscience.iop.org/article/10.7567/APEX.7.103001/pdf

Energy-delay performance of giant spin Hall effect switching for dense magnetic memory

This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual $V_{\mathrm {\mathbf {SS}}}$ signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a minimum operating voltage of 0.32 V while achieving the $6\sigma $ read stability yield. Compared with the previously proposed 9T SRAM cell, the proposed cell consumes 45% and 17% less energy per read and write operation, respectively, at the minimum operating voltage, and has a 12% smaller bit cell area.

Power-Gated 9T SRAM Cell for Low-Energy Operation

We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple layers (M4 and M6) incorporate an air gap integration scheme to deliver up to 17% RC benefit. Pitch Division patterning is introduced to deliver high yield capable interconnect layers with a minimum pitch of 52nm.

Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

We describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch stop. Metal-7 and Metal-8 use a low-k CDO. New materials and process optimization provide 13–18% capacitance improvement. Single-exposure patterning for 80nm pitch layers makes the process cost-effective.

D. Rao

Papers

Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing