P
P. Hentges
Researcher at Intel
Publications - 11
Citations - 1512
P. Hentges is an academic researcher from Intel. The author has contributed to research in topics: Logic gate & Non-volatile memory. The author has an hindex of 9, co-authored 11 publications receiving 1248 citations.
Papers
More filters
Proceedings ArticleDOI
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C. Auth,C. Allen,A. Blattner,Daniel B. Bergstrom,Mark R. Brazier,M. Bost,M. Buehler,V. Chikarmane,Tahir Ghani,Timothy E. Glassman,R. Grover,W. Han,D. Hanken,Michael L. Hattendorf,P. Hentges,R. Heussner,J. Hicks,D. Ingerly,Pulkit Jain,S. Jaloviar,Robert James,David Jones,J. Jopling,Subhash M. Joshi,C. Kenyon,Huichu Liu,R. McFadden,B. McIntyre,J. Neirynck,C. Parker,L. Pipes,Ian R. Post,S. Pradhan,M. Prince,S. Ramey,T. Reynolds,J. Roesler,J. Sandford,J. Seiple,Pete Smith,Christopher D. Thomas,D. Towner,T. Troeger,Cory E. Weber,P. Yashar,K. Zawadzki,Kaizad Mistry +46 more
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Proceedings ArticleDOI
45nm High-k + metal gate strain-enhanced transistors
C. Auth,Annalisa Cappellani,J.-S. Chun,A. Dalis,Alison Davis,Tahir Ghani,G. Glass,Timothy E. Glassman,Michael K. Harper,Michael L. Hattendorf,P. Hentges,S. Jaloviar,Subhash M. Joshi,Jason Klaus,K. Kuhn,D. Lavric,M. Lu,H. Mariappan,Kaizad Mistry,B. Norris,Nadia M. Rahhal-Orabi,Pushkar Ranade,J. Sandford,Lucian Shifren,V. Souw,K. Tone,F. Tambwe,A. Thompson,D. Towner,T. Troeger,P. Vandervoorn,Charles H. Wallace,J. Wiedemer,Christopher J. Wiegand +33 more
TL;DR: In this article, two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper.
Proceedings ArticleDOI
MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology
Oleg Golonzka,Juan G. Alzate,Umut Arslan,M. Bohr,P. Bai,Justin S. Brockman,Buford Benjamin,Chris Connor,Nilanjan Das,Brian S. Doyle,Tahir Ghani,Fatih Hamzaoglu,Philip E. Heil,P. Hentges,Rownak Jahan,David L. Kencke,Blake C. Lin,M. Lu,M. Mainuddin,Mesut Meterelliyoz,P. Nguyen,Dmitri E. Nikonov,O'brien Kevin P,J.O Donnell,Kaan Oguz,Ouellette Daniel G,Joodong Park,Pellegren James,Conor P. Puls,Pedro A. Quintero,Tofizur Rahman,A. Romang,M. Sekhar,A. Selarka,M. Seth,Smith Andrew,Smith Angeline K,Liqiong Wei,Christopher J. Wiegand,Z. Zhang,Kevin J. Fischer +40 more
TL;DR: Embedded NVM technology presented here achieves 200°C 10-year retention capability combined with>106 cycle endurance and high die yield, and is demonstrated on 7.2Mbit arrays.
Proceedings ArticleDOI
13.3 A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique
Liqiong Wei,Juan G. Alzate,Umut Arslan,Justin S. Brockman,Nilanjan Das,Kevin J. Fischer,Tahir Ghani,Oleg Golonzka,P. Hentges,Rawshan Jahan,Pulkit Jain,Blake C. Lin,Mesut Meterelliyoz,Jim OrDonnell,Conor P. Puls,Pedro A. Quintero,Tanaya Sahu,M. Sekhar,Ajay Vangapaty,Christopher J. Wiegand,Fatih Hamzaoglu +20 more
TL;DR: A write-verify-write (WvW) scheme and a programmable offset cancellation sensing technique that achieves a high-yield, high-performance and high-endurance 7Mb STT-MRAM arrays in a 22FFL FinFET technology is presented.
Proceedings ArticleDOI
13.2 A 3.6Mb 10.1Mb/mm 2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V
Pulkit Jain,Umut Arslan,M. Sekhar,Blake C. Lin,Liqiong Wei,Tanaya Sahu,Alzate-Vinasco Juan G,Ajay Vangapaty,Mesut Meterelliyoz,Nathan L. Strutt,Albert Chen,P. Hentges,Pedro A. Quintero,Chris Connor,Oleg Golonzka,Kevin J. Fischer,Fatih Hamzaoglu +16 more
TL;DR: The smallest ReRAM subarray density of 10.1Mb/mm2 is demonstrated, in a 22nm low-power process, and an optimized pulse-width (PW) voltage-current write-verify-write (PVC-WVW) sequence helps in mitigating endurance and variability.