N
N. Lazo
Researcher at Intel
Publications - 3
Citations - 232
N. Lazo is an academic researcher from Intel. The author has contributed to research in topics: Logic gate & Leakage (electronics). The author has an hindex of 3, co-authored 3 publications receiving 222 citations.
Papers
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Proceedings ArticleDOI
A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
C.-H. Jan,M. Agostinelli,M. Buehler,Zhanping Chen,S.-J. Choi,G. Curello,H. Deshpande,S. Gannavaram,Hafez Walid M,U. Jalan,M. Kang,Pramod Kolar,K. Komeyli,B. Landau,A. Lake,N. Lazo,Seung Hwan Lee,T. Leo,J. Lin,Nick Lindert,S. Ma,L. McGill,C. Meining,A. Paliwal,Joodong Park,K. Phoa,Ian R. Post,N. Pradhan,M. Prince,Abdur Rahman,J. Rizk,L. Rockford,G. Sacks,A. Schmitz,H. Tashiro,Curtis Tsai,P. Vandervoorn,J. Xu,L. Yang,J.-Y. Yeh,J. Yip,Kevin Zhang,Yuegang Zhang,P. Bai +43 more
TL;DR: The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently.
Proceedings ArticleDOI
A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors
C.-H. Jan,P. Bai,S. Biswas,M. Buehler,Zhanping Chen,G. Curello,S. Gannavaram,Hafez Walid M,Jun He,J. Hicks,U. Jalan,N. Lazo,J. Lin,Nick Lindert,C. Litteken,M. Jones,M. Kang,K. Komeyli,A. Mezhiba,S. Naskar,S. Olson,Joodong Park,Rachael J. Parker,L. Pei,Ian R. Post,N. Pradhan,Chetan Prasad,M. Prince,J. Rizk,G. Sacks,H. Tashiro,D. Towner,C. Tsai,Yih Wang,L. Yang,J.-Y. Yeh,J. Yip,Kaizad Mistry +37 more
TL;DR: A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products.
Proceedings ArticleDOI
Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing
D. Ingerly,A. Agrawal,R. Ascazubi,A. Blattner,M. Buehler,V. Chikarmane,B. Choudhury,F. Cinnor,C. Ege,C. Ganpule,Timothy E. Glassman,R. Grover,P. Hentges,J. Hicks,David Jones,A. Kandas,H. Khan,N. Lazo,K. S. Lee,H. Liu,A. Madhavan,R. McFadden,T. Mule,D. Parsons,P. Parthangal,Sudarshan Rangaraj,D. Rao,J. Roesler,A. Schmitz,Manvi Sharma,J. Shin,Y. Shusterman,N. Speer,P. Tiwari,Guotao Wang,P. Yashar,Kaizad Mistry +36 more
TL;DR: In this paper, the authors describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects.