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A. Schmitz
Researcher at Intel
Publications - 8
Citations - 218
A. Schmitz is an academic researcher from Intel. The author has contributed to research in topics: Reliability (semiconductor) & Capacitance. The author has an hindex of 5, co-authored 8 publications receiving 161 citations.
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Proceedings ArticleDOI
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology
Chetan Prasad,Lei Jiang,Dhruv Singh,M. Agostinelli,C. Auth,P. Bai,Travis Eiles,J. Hicks,Chia-Hong Jan,Kaizad Mistry,Sanjay Natarajan,B. Niu,Paul A. Packan,Daniel Pantuso,Ian R. Post,S. Ramey,A. Schmitz,Sell Bernhard,S. Suthram,J. Thomas,Curtis Tsai,P. Vandervoorn +21 more
TL;DR: In this article, the authors describe various measurements on self-heat performed on Intel's 22nm process technology and outline its reliability implications, comparing them to thermal modeling results and analytical data.
Proceedings ArticleDOI
Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing
D. Ingerly,A. Agrawal,R. Ascazubi,A. Blattner,M. Buehler,V. Chikarmane,B. Choudhury,F. Cinnor,C. Ege,C. Ganpule,Timothy E. Glassman,R. Grover,P. Hentges,J. Hicks,David Jones,A. Kandas,H. Khan,N. Lazo,K. S. Lee,H. Liu,A. Madhavan,R. McFadden,T. Mule,D. Parsons,P. Parthangal,Sudarshan Rangaraj,D. Rao,J. Roesler,A. Schmitz,Manvi Sharma,J. Shin,Y. Shusterman,N. Speer,P. Tiwari,Guotao Wang,P. Yashar,Kaizad Mistry +36 more
TL;DR: In this paper, the authors describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects.
Proceedings ArticleDOI
Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology
Flavio Griggio,J. Palmer,F. Pan,N. Toledo,A. Schmitz,I. Tsameret,Rahim Kasim,Gerald S. Leatherman,J. Hicks,A. Madhavan,J. Shin,Joseph M. Steigerwald,Yeoh Andrew W,C. Auth +13 more
TL;DR: Intrinsic TDDB reliability for Co/ low-k ILD meets the expectations and surpasses the capability of Cu/low- k ILD systems with E-field acceleration factor of ∼5 cm/MV using E-model fit.
Proceedings ArticleDOI
Silicon Reliability Characterization of Intel’s Foveros 3D Integration Technology for Logic-on-Logic Die Stacking
Chetan Prasad,Sunny Chugh,Hannes Greve,I-chen Ho,Enamul Kabir,Cheyun Lin,Mahjabin Maksud,Steven R. Novak,Benjamin J. Orr,K. W. Park,A. Schmitz,Zhizheng Zhang,Peng Bai,D. Ingerly,Emre Armagan,Hsinwei Wu,Patrick N. Stover,Lance C. Hibbeler,Michael P. O'Day,Daniel Pantuso +19 more
TL;DR: Simulations and data demonstrate mechanical strain safe zones around Through Silicon Vias (TSVs).
Proceedings ArticleDOI
A Reliability Overview of Intel’s 10+ Logic Technology
R. Grover,Tony Acosta,C. AnDyke,Emre Armagan,C. Auth,Sunny Chugh,K. Downes,Michael L. Hattendorf,Nathan Jack,Subhash M. Joshi,Rahim Kasim,Gerald S. Leatherman,Seung Hwan Lee,Che-Yun Lin,Madhavan Atul,H. Mao,A. Lowrie,G. Martin,G. McPherson,P. Nayak,Adam Neale,D. Nminibapiel,Benjamin J. Orr,J. Palmer,C. M. Pelto,Steven S. Poon,Ian R. Post,Tanmoy Pramanik,Abdur Rahman,S. Ramey,N. Seifert,K. Sethi,A. Schmitz,H. Wu,Yeoh Andrew W +34 more
TL;DR: This work provides a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology, a 10 nm technology featuring the third generation of Intel's FinFETs, seventh generation of strained silicon, and two thick-metal routing layers for low-resistance power routing.