High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

We examine mobility and saturation velocity in graphene on SiO2 above room temperature (300–500 K) and at high fields (∼1 V/μm). Data are analyzed with practical models including gated carriers, thermal generation, “puddle” charge, and Joule heating. Both mobility and saturation velocity decrease with rising temperature above 300 K, and with rising carrier density above 2×1012 cm−2. Saturation velocity is >3×107 cm/s at low carrier density, and remains greater than in Si up to 1.2×1013 cm−2. Transport appears primarily limited by the SiO2 substrate but results suggest intrinsic graphene saturation velocity could be more than twice that observed here.

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Mobility and saturation velocity in graphene on SiO2

We examine mobility and saturation velocity in graphene on SiO2 above room temperature (300-500 K) and at high fields (~1 V/um). Data are analyzed with practical models including gated carriers, thermal generation, "puddle" charge, and Joule heating. Both mobility and saturation velocity decrease with rising temperature above 300 K, and with rising carrier density above 2x10^12 cm^-2. Saturation velocity is >3x10^7 cm/s at low carrier density, and remains greater than in Si up to 1.2x10^13 cm^-2. Transport appears primarily limited by the SiO2 substrate, but results suggest intrinsic graphene saturation velocity could be more than twice that observed here.

Mobility and Saturation Velocity in Graphene on SiO2

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V/sub t/) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS).

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

To extend the lower bound of power supply to ultra-low voltages (06 V and below), we propose a dynamic-threshold voltage MOSFET (DTMOS) built on silicon-on-insulator (SOI) The threshold voltage of DTMOS drops as the gate voltage is raised, resulting in a much higher current drive than standard MOSFET at low power supply voltages On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low We provide experimental results and 2-D device and mixed-mode simulations to analyze DTMOS and compare its performance with a standard MOSFET These results verify excellent DC inverter characteristics down to V/sub dd/=02 V, and good ring oscillator performance down to 03 V for DTMOS >

A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V/sub dd/. On the other hand, V/sub t/ is high at V/sub gs/=0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V/sub dd/=0.5 V. >

A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

In this paper, we experimentally address the effect of a wide range of parameters on the high-field transport of inversion-layer electrons and holes. The studied parameters include substrate doping level, surface micro-roughness, vertical field strength, nitridation of the gate oxide, and device channel length. We employ special test structures built on Silicon-On-Insulator (SOI) and bulk wafers to accurately measure the high-field drift velocity of inversion-layer carriers. Our findings point to electron velocity overshoot at room temperature, dependence of electron and hole saturation velocities on nitridation of the gate oxide, dependence of the high-field drift velocity on the effective vertical field, and relative insensitivity of electron and hole mobility and saturation velocity to moderate surface roughness.

D. Sinitsky

Papers

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation

A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

High-field transport of inversion-layer electrons and holes including velocity overshoot

Simulation Of Floating Body Effect In SOI Circuits Using BSIM3SOI