The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

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Design of Analog CMOS Integrated Circuits

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >

/pdf/low-power-cmos-digital-design-52v6aautu5.pdf

Low-power CMOS digital design

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

Bandwidth-efficient data transmission over telephone and radio channels is made possible by the use of adaptive equalization to compensate for the time dispersion introduced by the channel Spurred by practical applications, a steady research effort over the last two decades has produced a rich body of literature in adaptive equalization and the related more general fields of reception of digital signals, adaptive filtering, and system identification. This tutorial paper gives an overview of the current state of the art in adaptive equalization. In the first part of the paper, the problem of intersymbol interference (ISI) and the basic concept of transversal equalizers are introduced followed by a simplified description of some practical adaptive equalizer structures and their properties. Related applications of adaptive filters and implementation approaches are discussed. Linear and nonlinear receiver structures, their steady-state performance and sensitivity to timing phase are presented in some depth in the next part. It is shown that a fractionally spaced equalizer can serve as the optimum receive filter for any receiver. Decision-feedback equalization, decision-aided ISI cancellation, and adaptive filtering for maximum-likelihood sequence estimation are presented in a common framework. The next two parts of the paper are devoted to a discussion of the convergence and steady-state properties of least mean-square (LMS) adaptation algorithms, including digital precision considerations, and three classes of rapidly converging adaptive equalization algorithms: namely, orthogonalized LMS, periodic or cyclic, and recursive least squares algorithms. An attempt is made throughout the paper to describe important principles and results in a heuristic manner, without formal proofs, using simple mathematical notation where possible.

https://ieeexplore.ieee.org/iel5/35/23767/01090994.pdf

Adaptive equalization

Conventional sub-Nyquist sampling methods for analog signals exploit prior information about the spectral support. In this paper, we consider the challenging problem of blind sub-Nyquist sampling of multiband signals, whose unknown frequency support occupies only a small portion of a wide spectrum. Our primary design goals are efficient hardware implementation and low computational load on the supporting digital processing. We propose a system, named the modulated wideband converter, which first multiplies the analog signal by a bank of periodic waveforms. The product is then low-pass filtered and sampled uniformly at a low rate, which is orders of magnitude smaller than Nyquist. Perfect recovery from the proposed samples is achieved under certain necessary and sufficient conditions. We also develop a digital architecture, which allows either reconstruction of the analog input, or processing of any band of interest at a low rate, that is, without interpolating to the high Nyquist rate. Numerical simulations demonstrate many engineering aspects: robustness to noise and mismodeling, potential hardware simplifications, real-time performance for signals with time-varying support and stability to quantization effects. We compare our system with two previous approaches: periodic nonuniform sampling, which is bandwidth limited by existing hardware devices, and the random demodulator, which is restricted to discrete multitone signals and has a high computational load. In the broader context of Nyquist sampling, our scheme has the potential to break through the bandwidth barrier of state-of-the-art analog conversion technologies such as interleaved converters.

/pdf/from-theory-to-practice-sub-nyquist-sampling-of-sparse-4swzjs0wes.pdf

From Theory to Practice: Sub-Nyquist Sampling of Sparse Wideband Analog Signals

High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described.

Time interleaved converter arrays

For pt.I see ibid., vol.SC-10, no.6, p.371-9 (1975). Describes techniques for performing A/D conversion compatibly with standard single-channel MOS technology. This second paper describes a two-capacitor successive approximation technique which, in contrast to the first, requires considerably less die area, is inherently monotonic in the presence of capacitor ratio errors, and which operates at somewhat lower conversion rate. Factors affecting accuracy and conversion rate are considered analytically. Experimental results from a monolithic prototype are presented; a resolution of eight bits was achieved with an A/D conversion time of 100 /spl mu/s. Used as a D/A convertor, a settling time of 12.5 /spl mu/s was achieved. The estimated total die size for a completely monolithic version including logic is 5000 mil/SUP 2/.

All-MOS charge-redistribution analog-to-digital conversion techniques. II

Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described. The code density test produces a histogram of the digital output codes of an ADC sampling a known input. The code density can be interpreted to compute the differential and integral nonlinearities, gain error, offset error, and internal noise. Conversion-rate and frequency-dependent behavior can also be measured.

Full-speed testing of A/D converters

A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET memory cell.

Modeling and simulation of insulated-gate field-effect transistor switching circuits

The third edition of Hodges and Jackson's Analysis and Design of Digital Integrated Circuits has been thoroughly revised and updated by a new co-author, Resve Saleh of the University of British Columbia The new edition combines the approachability and concise nature of the Hodges and Jackson classic with a complete overhaul to bring the book into the 21st century 
The new edition has replaced the emphasis on Bipolar with an emphasis on CMOS The book focuses on the latest CMOS technologies and uses standard deep submicron models throughout the book 
The material on memory has been expanded and updated As well the book now includes more on SPICE simulation and new problems that reflect recent technologies 
The emphasis of the book is on design, but it does not neglect analysis and has as a goal to provide enough information so that a student can carry out analysis as well as be able to design a circuit This book provides an excellent and balanced introduction to digital circuit design for both students and professionals 
Table of contents

1 Deep Submicron Digital IC Design
2 MOS Transistors
3 Fabrication, Layout and Simulation
4 MOS Inverter Circuits
5 Static MOS Gate Circuits
6 High-Speed CMOS Logic Design
7 Transfer Gate and Dynamic Logic Design
8 Semiconductor Memory Design
9 Additional Topics in Memory Design
10 Interconnect Design
11 Power Grid and Clock Design
Appendix A A Brief Introduction to Spice
Appendix B Bipolar Transistors and Circuits

David A. Hodges

Papers

Time interleaved converter arrays

All-MOS charge-redistribution analog-to-digital conversion techniques. II

Full-speed testing of A/D converters

Modeling and simulation of insulated-gate field-effect transistor switching circuits

Analysis and Design of Digital Integrated Circuits