Statistics for Spatial Data.

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

Historically, consumer computing products have moved to increasingly smaller form factors, from the personal computer, to the laptop, and now to devices such as smart phones and tablets. These products have a high amount of visibility, but in the background are datacenters solving problems beyond what can be solved by consumer devices. One of the first computers, ENIAC, was a massive machine that weighed 30 tons and occupied a full room to calculate artillery firing tables. Now it is possible to build a much more powerful system in a cubic millimeter form factor, but we still build warehouse-size systems, such as the "K computer", to solve complex problems like global weather simulation. 
Although advances in computing technology have greatly improved system capabilities and form factors, they have introduced problems in heat dissipation, reliability, and yield. Large scale systems are greatly affected by this, where their power usage is measured in megawatts, their reliability goal is running a mere 30 hours without system failure, and their processor count numbers in the hundreds of thousands. 
This thesis addresses these issues on four fronts. First, 3D-stacking technology coupled with near-threshold computing (NTC) is used to address heat dissipation. A 3D-stacked NTC system, Centip3De, is presented as a demonstration of this strategy, with a 75x decrease in processor power and a 5.1x improvement in energy efficiency. Next, system yield is addressed using a demonstrated in-situ performance monitoring technique, Safety Razor, which uses a novel time-to-digital converter with sub-picosecond calibration accuracy. Third, interconnect and system reliability is addressed with a failure tolerant interconnect fabric, Vicis, which disables faulty components to maintain reliability, tolerating fault rates of over 1 in 2,000 gates. Finally, stochastic computing is proposed as an error-tolerant form of computation for advanced VLSI processes. An example application of an image sensor array with built-in edge detection is investigated, with a power savings improvement of over 50% compared to a conventional approach.

Power, interconnect, and reliability techniques for large scale integrated circuits

We present an accelerator for seed-extension, a critical and computational intensive step in genome sequencing. The accelerator consists of a triangular array of 25×25 custom design processing elements implementing a string-independent automata. It achieves 2.46M reads/s, a ~1800x performance improvement, and 27x smaller silicon footprint compared to a Xeon E5420.

A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array

A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period. A reference ring oscillator has a plurality of reference unit cells arranged to form a reference ring, and generates a second output signal having a second oscillation period, each reference unit cell comprising components configured such that the second oscillation period provides an indication of a propagation delay through the pulse generation circuitry of the main unit cells of the main ring during the first oscillation period. Calculation circuitry then determines the clock node to output node delay of the flip-flop from the first oscillation period and the second oscillation period. This provides a particularly simple and accurate mechanism for calculating the clock node to output node delay of a flip-flop.

Measurement circuitry and method for measuring a clock node to output node delay of a flip-flop

A memory cell 36 within an integrated circuit memory is provided with an access controller 32 coupled to a first pass gate 38 and a second pass gate 40 . During a write access to the memory cell 38 both the first pass gate 38 and the second pass gate 40 are opened. During a read access, the first pass gate 38 is opened and the second pass gate 40 is closed. This asymmetry in the read and write operations permits an asymmetry in the gates forming the memory cell 36 thereby permitting changes to increase both read robustness and write robustness. The asymmetry in the design parameters of different gates can take the form of varying the gate length, the gate width and the threshold voltage so as to vary the conductance of different gates to suit their individual role within the memory cell 36 which is operating in the asymmetric manner provided by the separate word line signals driving read operations and write operations.

Integrated circuit memory access mechanisms

An integrated circuit memory 2 is provided with an array of memory cells 4 and power supply circuitry 10, 12 . Detected operating errors in malfunctioning memory cells 14 are identified using a built-in-self-test controller 34 . The power supply circuitry 10, 12 is then configured to alter the voltage supply to the malfunctioning memory cells 14 in an attempt to correct their operation. The voltage supply of the row containing the malfunctioning memory cell and the column containing the malfunctioning memory cell may both be altered. The voltage alteration may be an increase or a decrease in voltage supply depending upon the nature of the malfunction detected.

David Blaauw

Papers

Power, interconnect, and reliability techniques for large scale integrated circuits

A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array

Measurement circuitry and method for measuring a clock node to output node delay of a flip-flop

Integrated circuit memory access mechanisms

Integrated circuit memory power supply