Statistics for Spatial Data.

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

Moving-sum charge pump

A stacked voltage domain SRAM is proposed as an effective leakage reduction technique where bit-cell arrays are split into two voltage domains (top and bottom) connecting in series between VDD and GND to generate a subthreshold retention voltage directly from a nominal supply with no area penalty or efficiency loss compared to the conventional voltage regulator approach. The Zigzag 8T bit-cell structure is chosen with an optimal transistor sizing to balance among hold stability, leakage, and area density. SRAM peripherals remains at full supply domain resulting in super-cutoff read for improved sensing margin and word-line overdrive for better write margin. A novel array swapping mechanism with a comprehensive timing control ensure stable access to arbitrary arrays within one system clock cycle. The proposed SRAM achieves 1.03-pW/b leakage at 0.58 V in 40 nm.

A 40-nm Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent IoT Sensors

A sub-nW voltage reference is presented that provides inherently low process variation and enables trim-free operation for low-dropout regulators and other applications in nW microsystems. Sixty chips from three different wafers in 180 nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124 ppm/° C. from −40° C. to 85° C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114 pW at 25° C.

Variation-tolerant voltage reference

IoT sensors are in rising demand and they often require low power, yet high precision measurements. Under constrained energy, Nyquist-rate SAR ADCs are typically used for readout as they are energy efficient and easy to multiplex across many sensors. However, achieving high precision (>14b) in SAR ADCs is challenging as all factors limiting performance (resolution, mismatch, and noise) must be simultaneously addressed with minimal energy impact. In this paper, we present an energy-efficient, capacitor-array-assisted cascaded charge-injection SAR ADC (c-ciSAR) with 17b nominal resolution (14.14b ENOB) that achieves a 184.9dB Schreier FoM (SFoM) and 4.32fJ/conv with a 1V supply in 0.18μm CMOS. The ADC deploys a combination of techniques to improve resolution, mismatch, and noise performance while remaining energy-efficient, namely: 1) hybridization of a capacitor-array DAC (CDAC) with chargeinjection-cell (ci-cell) based DACs (ciDACs) to achieve high resolution and flexible programmability; 2) direct analog DAC mismatch compensation and repeated LSB decisions that leverage flexible programmability; 3) a noise-efficient charge-domain preamplifier for comparator (1.66 NEF) and SNR extended ci-cell; and 4) ±2?VDD signal sampling with pre-sampling MSB decision.

14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC

One of the critical challenges in today's high performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools are effective at analyzing and identifying noise in the post-route design stage when detailed parasitic information is available. However, noise problems identified at this stage of design cycle are very difficult to fix due to the limited flexibility in the design and may, cause additional iterations of routing and placement, adding costly delays to time-to-market. In this paper we introduce an estimated, congestion-based pre-route noise analysis approach to identify post-route noise failures before the actual detailed route is completed. We introduce new methods to estimate the RC characteristics of victim and aggressor lines, their coupling capacitances and the aggressor transition times before routing is performed. The approach is based on congestion information obtained from a global router. Since the exact location and relative position of wires in the design is not yet available at this point, we propose a novel probabilistic method for capacitance extraction. We present results on two high performance microprocessors in 0.18 /spl mu/ technology that demonstrate the effectiveness of the proposed approach.

David Blaauw

Papers

Moving-sum charge pump

A 40-nm Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent IoT Sensors

Variation-tolerant voltage reference

14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC

Pre-route noise estimation in deep submicron integrated circuits