Statistics for Spatial Data.

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

Power consumption is becoming worse with every technology generation. While there has been much research in recent years proposing design methods addressing this issue, one of the most efficient approaches is to reduce supply voltage, which can help mitigate both dynamic and static power consumption. 
In our research, we found the optimal voltage (Vmin) for energy efficiency in CMOS technology. We analyzed the different factors affecting Vmin and find that Vmin usually lies in subthreshold voltage regime. The increased sensitivity of subthreshold switching current to process variation poses a significant design challenge. We investigated the impact of subthreshold variation on circuit performance and energy consumption in a statistical manner and proposed certain design guidelines to mitigate variation.
To verify the high energy efficiency of subthreshold operation, we designed and fabricated two subthreshold processors in 0.13um technology, specifically, the Subliminal 1 and Subliminal 2 processors. Measurements confirm 2.60pJ per instruction efficiency for the Subliminal 1. However, we also found that the on-chip SRAM was the energy consumption bottleneck. Therefore, we designed the first sub-200mV compact 6-T SRAM. It was fabricated in a commercial 0.13um CMOS technology and silicon measurements shows that all 24 dies measured were fully functional and a typical die operates from 1.2V to 193mV. This could be further extended to sub-170mV with 2% bit redundancy.
The downside of voltage scaling into subthreshold is the considerable performance loss. To address this issue, we proposed a novel micro-architecture that combines chip multi-processing and subthreshold techniques. By tuning the supply voltage and threshold voltage of the L1 cache and the processor core independently, we found that having multiple cores sharing one faster local L1 provides the best energy efficiency. In particular, SPLASH2 benchmarks show about a 53% energy improvement over the traditional CMP approach (about 70% over a single core machine).

Ultra-low power processor design using sub-threshold design techniques

Despite recent improvements in nanopore basecalling accuracy, germline variant calling of small insertions and deletions (INDELs) remains poor. Although precision and recall for single nucleotide polymorphisms (SNPs) now regularly exceeds 99.5%, INDEL recall at relatively high coverages (85×) remains below 80% for standard R9.4.1 flow cells [22, 23, 31]. Current nanopore variant callers work in two stages: an efficient pileup-based method identifies candidates of interest, and then a more expensive full-alignment model provides the final variant calls. Most false negative INDELs are lost during the first (pileup-based) step, particularly in low-complexity repeated regions. We show that read phasing and realignment can recover a significant portion of INDELs lost during this stage. In particular, we extend Needleman-Wunsch affine gap alignment by introducing new gap penalties for more accurately aligning repeated n-polymer sequences such as homopolymers (n = 1) and tandem repeats (2 ≤ n ≤ 6). On our dataset with 60.6× coverage, haplotype phasing improves INDEL recall in all evaluated high confidence regions from 63.76% to 70.66% and then nPoRe realignment improves it further to 73.04%, with no loss of precision.

nPoRe: n-Polymer Realigner for improved pileup variant calling

http://ma.ecsdl.org/content/MA2006-02/24/1203.full.pdf

David Blaauw

Papers

Ultra-low power processor design using sub-threshold design techniques

nPoRe: n-Polymer Realigner for improved pileup variant calling

Design and Optimization of Hybrid Power Systems for Fully Implantable Medical Devices

Nuclear Hydrogen Production: An Overview

Digital Circuit Innovations