David Blaauw

TL;DR: This work proposes a heuristic approach to compute the worst-case aggressor alignment which maximizes the victim receiver output arrival time and uses a novel cumulative gate overdrive voltage (CGOV) metric to model the victim Receiver output transition.

TL;DR: The concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode, is introduced, which improves standby leakage reduction with acceptable area penalty and no impact on active mode operation.

TL;DR: An architectural simulator design is presented that incorporates a circuit modeling capability, permitting architectural-level simulations that react to circuit characteristics on a cycle-by-cycle basis and shows that the careful application of circuit simulation optimizations and simulation sampling techniques permit high levels of detail with sufficient speed to examine entire workloads.

TL;DR: A novel design time body bias selection framework for parametric yield optimization while reducing testing costs is proposed and uses a feature extraction technique to explore the underlying similarity between the gates for effective clustering.

TL;DR: A new circuit technique for on-chip communication, the edge encoding technique, to reduce the energy consumption in multi-cycle interconnects by desynchronizing the edges of rising and falling transitions is proposed.