D
David Blaauw
Researcher at University of Michigan
Publications - 792
Citations - 32719
David Blaauw is an academic researcher from University of Michigan. The author has contributed to research in topics: CMOS & Low-power electronics. The author has an hindex of 87, co-authored 750 publications receiving 29855 citations. Previous affiliations of David Blaauw include Texas A&M University & University of Illinois at Urbana–Champaign.
Papers
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Journal ArticleDOI
Early probabilistic noise estimation for capacitively coupled interconnects
TL;DR: A probabilistic preroute noise analysis approach to identify postroute noise failures before the actual detailed route is completed and new methods to estimate the RC characteristics of victim and aggressor lines, their coupling capacitances, and the aggressor transition times before routing is performed are introduced.
Proceedings ArticleDOI
A 5.8nW, 45ppm/°C On-Chip CMOS Wake-up Timer Using a Constant Charge Subtraction Scheme.
TL;DR: A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators, enabling low power operation.
Proceedings ArticleDOI
A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications
Seokhyeon Jeong,Wanyeong Jung,Dongsuk Jeon,Omer Berenfeld,Hakan Oral,Grant H. Kruger,David Blaauw,Dennis Sylvester +7 more
TL;DR: An 8-bit sub-ranging SAR ADC designed for bursty signals having long time periods with small code spread is presented, saving previous sample's MSB voltage and reuses it throughout subsequent conversions, reducing energy consumed in the comparator and digital logic and yielding total energy savings of 2.6×.
Proceedings ArticleDOI
Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence
TL;DR: It is shown that the optimal way to select samples, to capture intra-die variation accurately, is according to the probability distribution function of total process variation, which means reduced sample size to meet target accuracy for computing leakage distribution due to the inter-die component only when compared to random selection of samples.
Journal ArticleDOI
Fast on-chip inductance simulation using a precorrected-FFT method
Haitian Hu,David Blaauw,Vladimir Zolotov,Kaushik Gala,Min Zhao,Rajendran Panda,Sachin S. Sapatnekar +6 more
TL;DR: In terms of accuracy, memory, and speed, it is shown that the precorrected-FFT method is an excellent approach for simulating on-chip inductance in a large circuit.