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David Blaauw

Researcher at University of Michigan

Publications -  792
Citations -  32719

David Blaauw is an academic researcher from University of Michigan. The author has contributed to research in topics: CMOS & Low-power electronics. The author has an hindex of 87, co-authored 750 publications receiving 29855 citations. Previous affiliations of David Blaauw include Texas A&M University & University of Illinois at Urbana–Champaign.

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Proceedings ArticleDOI

Hierarchical analysis of power distribution networks

TL;DR: A new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid, and a novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superiorSparsification for a specified error.
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Correction to “A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation”

TL;DR: This paper applies Razor to a 32 bit ARM processor with a micro-architecture design that has balanced pipeline stages with critical memory access and clock-gating enable paths, and shows potential for parametric yield improvement through energy-efficient operation using Razor.
Proceedings ArticleDOI

Vicis: a reliable network for unreliable silicon

TL;DR: This work presents Vicis, an ElastIC-style NoC that can tolerate the loss of many network components due to wearout induced hard faults, and shows that with stuck-at fault rates as high as 1 in 2000 gates, Vicis will continue to operate with approximately half of its routers still functional and communicating.
Journal ArticleDOI

A Modular 1 mm $^{3}$ Die-Stacked Sensing Platform With Low Power I $^{2}$ C Inter-Die Communication and Multi-Modal Energy Harvesting

TL;DR: A self-adapting power management unit is proposed for efficient battery voltage down conversion for wide range of battery voltages and load current and adapts itself by monitoring energy harvesting conditions and harvesting sources.
Proceedings ArticleDOI

Design and analysis of power distribution networks in PowerPC/sup TM/ microprocessors

TL;DR: A methodology for the design and analysis of power grids in the PowerPC™ microprocessors covering the need for power grid analysis across all stages of the design process is presented.