Statistics for Spatial Data.

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

Over the last decade, advances in high-throughput sequencing and the availability of portable sequencers have enabled fast and cheap access to genetic data. For a given sample, sequencers typically output fragments of the DNA in the sample. Depending on the sequencing technology, the fragments range from a length of 150–250 at high accuracy to lengths in few tens of thousands but at much lower accuracy. Sequencing data is now being produced at a rate that far outpaces Moore's law and poses significant computational challenges on commodity hardware. To meet this demand, software tools have been extensively redesigned and new algorithms and custom hardware have been developed to deal with the diversity in sequencing data. However, a standard set of benchmarks that captures the diverse behaviors of these recent algorithms and can facilitate future architectural exploration is lacking. To that end, we present the GenomicsBench benchmark suite which contains 12 computationally intensive data-parallel kernels drawn from popular bioinformatics software tools. It covers the major steps in short and long-read genome sequence analysis pipelines such as basecalling, sequence mapping, de-novo assembly, variant calling and polishing. We observe that while these genomics kernels have abundant data level parallelism, it is often hard to exploit on commodity processors because of input-dependent irregularities. We also perform a detailed microarchitectural characterization of these kernels and identify their bottlenecks. GenomicsBench includes parallel versions of the source code with CPU and GPU implementations as applicable along with representative input datasets of two sizes - small and large.

GenomicsBench: A Benchmark Suite for Genomics

A system and method is provided that improves the propagation characteristics of an electrical conducting signal wire on an integrated circuit. The system includes a pair of parallel shielding wires positioned on opposite longitudinal sides of the signal wire. A shielding signal is applied to the shielding wires. The shielding signal is out of phase with the signal of interest propagated on the signal wire.

Actively-shielded signal wires

Standby power frequently dominates the power budget of battery-operated ultralow power sensor nodes. Reducing standby power is therefore a key challenge for further power reduction. Applying known circuit techniques for standby power reduction is challenging since standby power of state-of-the-art sensor node systems is now on the order of nanowatts or less. Hence, the overhead of any leakage reduction technique quickly overshadows any gains. This brief proposes an efficient implementation method for super cutoff CMOS that exploits the unique conditions of power gating to enable a highly efficient charge pump design. The proposed techniques are applied to logic blocks and memory devices. For a very low initial standby power value of tens of picowatts, standby power reduction of up to 19.3 × and 29% is achieved for logic blocks and memory, respectively.

Achieving Ultralow Standby Power With an Efficient SCCMOS Bias Generator

Dual-junction GaAs photovoltaic (PV) cells and modules at submillimeter scale are demonstrated for efficient wireless power transfer for Internet of Things and bio-implantable applications under low-flux illumination. The dual-junction approach meets demanding requirements for these applications by increasing the output voltage per cell with reduced area losses from isolation and interconnects. A single PV cell (150 μm × 150 μm) based on the dual-junction design demonstrates power conversion efficiency above 22% with greater than 1.2 V output voltage under low-flux 850 nm near-infrared LED illumination at 6.62 μW/mm2, which is sufficient for the batteryless operation of miniaturized CMOS IC chips. The output voltage of dual-junction PV modules with four series-connected cells demonstrates greater than 5 V for direct battery charging while maintaining a module power conversion efficiency of more than 23%.

Dual-Junction GaAs Photovoltaics for Low Irradiance Wireless Power Transfer in Submillimeter-Scale Sensor Nodes

A system and method for manipulating waveforms, including transaction cancellation, in parallel time-warp simulation of circuits, such as those modeled in VHDL. Events waveforms for each output of a processor are organized by the simulation time (ST) of the events which created them and by the simulation time (RT) at which they are to be effective. A phantom buffer provides a linked list of events and associated transactions cancelled as a result of insertion of a new event in said chain of events. Rollback of a cancelled event waveform is done by restoring to the linked lists selected events and transactions from the phantom buffer.

David Blaauw

Papers

GenomicsBench: A Benchmark Suite for Genomics

Actively-shielded signal wires

Achieving Ultralow Standby Power With an Efficient SCCMOS Bias Generator

Dual-Junction GaAs Photovoltaics for Low Irradiance Wireless Power Transfer in Submillimeter-Scale Sensor Nodes

Waveform manipulation in time warp simulation