Showing papers by "David Esseni published in 2002"

Study of low field electron transport in ultra-thin single and double-gate SOI MOSFETs

Abstract: This paper studies the dependence on silicon film thickness (T/sub SI/) of the electron mobility in Single- (SG) and Double-Gate (DG) Ultra-Thin (UT) SOI MOSFETs. A comprehensive model was developed, including acoustic and optical phonon scattering and the scattering with possible interface states and microscopic roughness at both interfaces. The T/sub SI/ dependence of the effective mobility (/spl mu//sub eff/) predicted by simulations is, at moderate inversion densities (N/sub inv/), weaker than that observed in experiments. We analyze the physical origin of this discrepancy, with particular attention to the phonon limited mobility. Our results indicate that scattering with surface optical phonons is strongly enhanced in UT silicon layers and that it may help explain the experimental behavior of /spl mu//sub eff/.

Damage generation and location in n- and p-MOSFETs biased in the Substrate-Enhanced Gate Current regime

Abstract: This paper analyzes MOSFET degradation in the regime of hot carrier injection enhanced by substrate bias Substrate-Enhanced Gate Current (SEGC). The results are compared with the damage generated during conventional Channel Hot Carrier (CHC) stress experiments. The investigation was carried out on state of the art n/sup +/-poly n-MOSFETs and p/sup +/-poly p-MOSFETs, and it includes both a detailed characterization of standard electrical parameters (i.e., threshold voltage, drain current and linear transconductance) and a spatial profiling of stress-induced interface states. Our results reveal that the application of a substrate bias enhances degradation on both n-MOS and p-MOS devices and spreads toward the center of the channel the spatial profile of the damage. For a given gate current and oxide field in the injection region, the total amount of the generated damage is quite similar in both cases, but in the SEGC regime, the spatial distribution of generated traps is more distributed along the channel.

An Improved Model for Electron Mobility Degradation by Remote Coulomb Scattering in Ultra-Thin Oxide MOSFETs

Abstract: This paper presents a new model for the electron mobility degradation in MOSFETs due to Remote Coulomb Scattering. We improved previous theoretical treatments by including screening in polysilicon and removing the approximation of quantum limit transport. Our results demonstrate that the ingredients included in our model are of remarkable quantitative importance.

A new high injection efficiency non-volatile memory cell: BipFlash

Abstract: This paper presents a novel non-volatile memory cell architecture (BipFlash), which improves remarkably injection efficiency over that obtained with conventional channel hot-electron programming. The cell concept is validated by means of numerical device simulations including accurate Monte Carlo analysis of hot carrier transport and injection in the floating gate. Design strategies to achieve optimum device performance and possible solutions for cell layout and array organization are also discussed. We show that the superior performance of BipFlash in terms of injection efficiency can be traded to achieve either very low voltage, low power or high-speed operation.

Spectroscopic analysis of trap assisted tunneling in thin oxides by means of substrate hot electron injection experiments

Abstract: In this paper we present experimental evidence of the contribution of stress induced traps to Substrate Hot Electron (SHE) injection. We investigate the energy distribution of traps generated by Fowler Nordheim (FN) and Hot Electron (HE) stress with the aid of simulations and experiments. Results suggest that HE stress generates more oxide traps at high energy with respect to FN stress. The comparison between experiments and simulations also provides a new additional evidence of the inelastic nature of the trap assisted tunneling mechanism.

Ultra-thin SOI transistors for ultimate CMOS technology: Fundamental properties and application perspectives

Abstract: In this paper we present experimental data or electron mobility in Ultra-Thin SOI MOSFETs operating in Single- and Double-Gate Mode Mobility is measured for silicon thicknesses down to 5nm and for temperatures ranging from 225K to 375K At large inversion densities (Ninv) ultra-thin SOI exhibit higher mobility than heavily doped bulk MOS and a small dependence of mobility on silicon thickness (TSI) However, at small Ninv the mobility is clearly reduced for decreasing TSI, possibly due to enhanced phonon scattering in the thin quantum well Compared to Single-Gate, a modest but unambiguous mobility improvement is observed in Double-Gate mode, for silicon films around 10nm and small inversion densities The mobility increase is more pronounced at low temperatures