David S. Lee

TL;DR: This study examines the single-event response of the Xilinx 28 nm Kintex-7 FPGA irradiated with heavy ions and describes an unconventional single event latch-up signature observed during testing.

TL;DR: This paper presents a technique for extracting MCUs statistically from radiation test data and uses this technique to extract MCU information from a 28-nm FPGA that uses interleaving to protect the configuration memory.

TL;DR: In this paper, low-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate.

TL;DR: This paper investigates the improvements in reliability of a LEON3 soft processor operating on a SRAM-based FPGA when using triple-modular redundancy and other processor-specific mitigation techniques and demonstrates an average improvement of 10×.

TL;DR: In this article, the single event response of Xilinx 16nm FinFET UltraScale+ FPGA and MPSoC device families is examined, including single event latch-up, single event upsets in configuration SRAM, BlockRAM memories, and flip-flops.