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David W Parent

Researcher at San Jose State University

Publications -  55
Citations -  333

David W Parent is an academic researcher from San Jose State University. The author has contributed to research in topics: Transistor & Metalorganic vapour phase epitaxy. The author has an hindex of 8, co-authored 53 publications receiving 299 citations. Previous affiliations of David W Parent include University of California, Santa Cruz & University of Connecticut.

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Proceedings ArticleDOI

Teaching design of experiments and statistical analysis of data through laboratory experiments

TL;DR: The Advanced Thin Film Processes (ATP) course at San Jose State University as mentioned in this paper integrates fabrication of thin films with the design of experiment and statistical analysis of data, and students work through six multi-week modules.
Journal Article

Microelectronics Process Engineering at San Jose State University: A Manufacturing-Oriented Interdisciplinary Degree Program

TL;DR: San Jose State University's new interdisciplinary curriculum in Microelectronics Process Engineering is described in this paper, which emphasizes hands-on thin-film fabrication experience, manufacturing methods such as statistical process control, and fundamentals of materials science and semiconductor device physics.
Journal ArticleDOI

Photoassisted MOVPE grown (n)ZnSe/(p+)GaAs heterojunction solar cells

TL;DR: In this article, the electrical properties of (n)ZnSe/(p þ )GaAs heterostructure solar cells were reported by depositing an n-type ZnSe epilayer using photo assisted metal organic vapor phase epitaxy on p þ type GaAs (1 0 0) substrates.
Proceedings ArticleDOI

Compact digital implementation of a quadratic integrate-and-fire neuron

TL;DR: A compact fixed-point digital implementation of a quadratic integrate-and-fire (QIF) neural model was developed, and equations were derived to determine the minimum number of bits the digital QIF model requires to represent all four states and control the switching threshold of the output voltage.
Proceedings ArticleDOI

An analog circuit implementation of a quadratic integrate and fire neuron

TL;DR: A hardware version of the quadratic integrate and fire neural model, which differs from the more common integrate andFire neuron in that the model, and thus the hardware, intrinsically generate spikes.