D
David Z. Pan
Researcher at University of Texas at Austin
Publications - 557
Citations - 12677
David Z. Pan is an academic researcher from University of Texas at Austin. The author has contributed to research in topics: Computer science & Routing (electronic design automation). The author has an hindex of 50, co-authored 496 publications receiving 10182 citations. Previous affiliations of David Z. Pan include University of California, Los Angeles & Fudan University.
Papers
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Proceedings ArticleDOI
Clock power minimization using structured latch templates and decision tree induction
Samuel I. Ward,Natarajan Viswanathan,Nancy Zhou,Chin Ngai Sze,Zhuo Li,Charles J. Alpert,David Z. Pan +6 more
TL;DR: A redundancy removal approach using set-theoretic annotation is proposed demonstrating it is possible to remove over 99% of the templates with no information loss, and a decision tree induction algorithm with novel impurity metric enables extremely fast template selection during the clock optimization stage of a modern physical design flow.
Journal ArticleDOI
Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations
TL;DR: In this paper, a contact-edge roughness model based on the power spectral density function is proposed, which is a function of rms edge roughness, correlation length, and fractal dimension, and analyzed the impact of both random CER and systematic variation on the S/D contact resistance and the device saturation current.
Proceedings ArticleDOI
Layout level timing optimization by leveraging active area dependent mobility of strained-silicon devices
TL;DR: This work proposes a new methodology to exploit the dependence of mobility of a SS MOSFET device on its poly-to-poly distance to achieve cycle time reduction of a design at the layout level without requiring any optimization iterations.
Proceedings ArticleDOI
UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper)
TL;DR: In this paper, a parallelization framework for modern FPGA global placement, UTPlaceF 3.0, is presented to boost the performance of a state-of-the-art quadratic placer with only small quality degradation.
Proceedings ArticleDOI
Application-aware NoC design for efficient SDRAM access
Wooyoung Jang,David Z. Pan +1 more
TL;DR: This paper proposes an application-aware networks-on-chip (NoCs) design for an efficient SDRAM access, which can consider memory latency demands and memory access granularities in various applications and significantly improves memory latency and overall memory latency.