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David Z. Pan

Researcher at University of Texas at Austin

Publications -  557
Citations -  12677

David Z. Pan is an academic researcher from University of Texas at Austin. The author has contributed to research in topics: Computer science & Routing (electronic design automation). The author has an hindex of 50, co-authored 496 publications receiving 10182 citations. Previous affiliations of David Z. Pan include University of California, Los Angeles & Fudan University.

Papers
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Proceedings ArticleDOI

Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction

TL;DR: This paper proposes a fast link insertion methodology which does not require selecting empirical parameters for link insertion and also incrementally considers the effect of previously inserted links before choosing the next link.
Journal ArticleDOI

Lithography hotspot detection using a double inception module architecture

TL;DR: This work proposes a lithography hotspot detection framework using a double inception module structure that performs better in both accuracy and false alarms by widening the conventional stacked structure to benefit feature extraction and using global average pooling to keep the spatial information.
Proceedings ArticleDOI

TILA: Timing-Driven Incremental Layer Assignment

TL;DR: A timing driven incremental layer assignment tool, TILA, to reassign layers among routing segments of critical nets and non-critical nets and Lagrangian relaxation techniques are proposed to iteratively provide consistent layer/via assignments.
Journal ArticleDOI

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter

TL;DR: This article presents an incremental two-step capacitance-to-digital converter (CDC) with a time-domain TD modulator, which replaces the operational transconductance amplifier (OTA)-based active- active-RC integrator by a voltage-controlled oscillator (VCO)-based integrator, which is mostly digital and low-power.
Proceedings ArticleDOI

DREAMPlace 3.0: multi-electrostatics based robust VLSI placement with region constraints

TL;DR: This work proposes a versatile and robust placer to solve region-constrained placement problems with better solution quality and faster convergence and adopts self-adaptive quadratic density penalty and entropy injection techniques to automatically accelerate and stabilize the nonlinear optimization.