다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

Data Mining Practical Machine Learning Tools and Techniques

The reference human genome sequence set the stage for studies of genetic variation and its association with human disease, but epigenomic studies lack a similar reference. To address this need, the NIH Roadmap Epigenomics Consortium generated the largest collection so far of human epigenomes for primary cells and tissues. Here we describe the integrative analysis of 111 reference human epigenomes generated as part of the programme, profiled for histone modification patterns, DNA accessibility, DNA methylation and RNA expression. We establish global maps of regulatory elements, define regulatory modules of coordinated activity, and their likely activators and repressors. We show that disease- and trait-associated genetic variants are enriched in tissue-specific epigenomic marks, revealing biologically relevant cell types for diverse human traits, and providing a resource for interpreting the molecular basis of human disease. Our results demonstrate the central role of epigenomic information for understanding gene regulation, cellular differentiation and human disease.

Integrative analysis of 111 reference human epigenomes

“Unpaired Image-to-Image Translation using Cycle-Consistent Adversarial Networks”の学習報告

This paper reports two sets of important results in our exploration of an interconnect-centric design flow for deep submicron (DSM) designs: (i) We obtain efficient yet accurate wiring area estimation models for optimal wire sizing (OWS). We also propose a simple metric to guide area-efficient performance optimization; (ii) Guided by our interconnect estimation models, we study the interconnect architecture planning problem for wire-width designs. We achieve a rather surprising result which suggests that two pre-determined wire widths per metal layer are sufficient to achieve near-optimal performance. This result will greatly simplify the routing architecture and tools for DSM designs. We believe that our interconnect estimation and planning results will have a significant impact on DSM designs.

/pdf/interconnect-estimation-and-planning-for-deep-submicron-4zitsdyzl7.pdf

Interconnect estimation and planning for deep submicron designs

In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first propose a compact post-OPC litho-metric for a detailed router based on statistical characterization. We characterize the interferences among weak grids filled with one of predefined litho-prone shapes (e.g., jog-corner, via, line-end). Our litho-metric derived from the characterization shows high fidelity to total edge placement error (EPE) in large scale, compared with Calibre-OPC/ORC. As a chip itself is in the largest scale, ELIAD powered by the proposed metric can enhance the overall post-OPC printed silicon image. Experimental results on 65 nm industrial circuits show that ELIAD outperforms a ripup/rerouting approach such as RADAR [17] with 8times more EPE hotspot reduction and 12times speedup. Also, compared with a conventional detailed router, ELIAD is only about 50% slower.

/pdf/eliad-efficient-lithography-aware-detailed-router-with-40swzmn3b4.pdf

ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction

As minimum feature size and pitch spacing further decrease in advanced technology nodes, many new design constraints and challenges are introduced, such as regularity, middle of line (MOL) structures, and pin-access challenges. In this work, we propose a comprehensive study on standard cell layout regularity and pin access optimization. Given irregular cell layout from old technology nodes, our cell optimization tool can search unidirectional migrated result where the self-aligned double patterning (SADP) and MOL based design constraints are satisfied, and the pin-accessibility is optimized. This problem is formulated as a general integer linear programming (ILP), which may suffer from long runtime for some large standard cell cases. Therefore, we also develop a set of hybrid techniques to quickly search for high-quality solutions. The experimental results demonstrate the effectiveness of our approaches.

https://www.cerc.utexas.edu/utda/publications/C174.pdf

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line

In this work, we propose an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design optimization methodology to alleviate TSV interfacial crack problems in 3D ICs. First, we analyze TSV interfacial crack at TSV/dielectric liner interface caused by TSV-induced thermo-mechanical stress. Then, we explore the impact of TSV placement in conjunction with various associated structures such as landing pad and dielectric liner on TSV interfacial crack. Next, we present a full-chip TSV interfacial crack analysis methodology based on design of experiments (DOE) and response surface method (RSM). Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.

/pdf/full-chip-through-silicon-via-interfacial-crack-analysis-and-3ad5r3t2hd.pdf

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC

Optical proximity correction (OPC) is one of the most important techniques in today’s optical lithography-based manufacturing process. Although the most widely used model-based OPC is expected to achieve highly accurate correction, it is also known to be extremely time-consuming. This paper proposes a regression model for OPC using a hierarchical Bayes model (HBM). The goal of the regression model is to reduce the number of iterations in model-based OPC. Our approach utilizes a Bayes inference technique to learn the optimal parameters from given data. All parameters are estimated by the Markov Chain Monte Carlo method. Experimental results show that utilizing HBM can achieve a better solution than other conventional models, e.g., linear regression-based model, or nonlinear regression-based model. In addition, our regression results can be used as the starting point of conventional model-based OPC, through which we are able to overcome the runtime bottleneck.

David Z. Pan

Papers

Interconnect estimation and planning for deep submicron designs

ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC

Optical proximity correction with hierarchical Bayes model