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David Z. Pan

Researcher at University of Texas at Austin

Publications -  557
Citations -  12677

David Z. Pan is an academic researcher from University of Texas at Austin. The author has contributed to research in topics: Computer science & Routing (electronic design automation). The author has an hindex of 50, co-authored 496 publications receiving 10182 citations. Previous affiliations of David Z. Pan include University of California, Los Angeles & Fudan University.

Papers
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Journal ArticleDOI

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography

TL;DR: This paper proposes a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design, and shows that, with negligible impact on critical path delay, this framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition.
Proceedings ArticleDOI

Design for manufacturability and reliability for TSV-based 3D ICs

TL;DR: Some key design for manufacturability and reliability challenges and possible solutions for TSV-based 3D IC integration, as well as future research directions are discussed.
Proceedings ArticleDOI

LithoROC: lithography hotspot detection with explicit ROC optimization

TL;DR: This work proposes the use of the area under the ROC curve (AUC), which provides a more holistic measure for imbalanced datasets compared with the previous methods, and proposes the surrogate loss functions for direct AUC maximization as a substitute for the conventional cross-entropy loss.
Proceedings ArticleDOI

Wafer Map Defect Patterns Classification using Deep Selective Learning

TL;DR: This paper proposes a novel methodology for wafer map defect pattern classification using deep selective learning that features an integrated reject option where the model chooses to abstain from predicting a class label when misclassification risk is high, providing a trade-off between prediction coverage and mis classification risk.
Proceedings ArticleDOI

Hardware-software co-design of slimmed optical neural networks

TL;DR: This work designs a novel slimmed architecture for realizing optical neural network considering both its software and hardware implementations and shows a more area-efficient architecture which uses a sparse tree network block, a single unitary block and a diagonal block for each neural network layer.