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Showing papers by "Dinesh K. Sharma published in 2010"


Journal ArticleDOI
TL;DR: In this article, the authors proposed a bottom spacer fin-shaped field-effect transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements.
Abstract: For the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, power-delay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electrothermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications.

46 citations


Proceedings ArticleDOI
01 Nov 2010
TL;DR: In this article, a novel energy-efficient current-mode signaling scheme (CMS) for long on-chip interconnects was described. But the scheme was fabricated in 180nm process.
Abstract: This paper describes a novel energy-efficient current-mode signaling scheme (CMS scheme) for long on-chip interconnects. The scheme was fabricated in 180nm process. Measurement results show that the proposed 6mm long link offers 22% improvement in delay with 81% lower energy consumption at 0.62Gbps over the voltage-mode scheme. The proposed scheme offers 20% improvement in power-delay-product over the CMS scheme proposed by Katoch et al. in [5]. Furthermore, it is less sensitive to intra-die variations.

12 citations


Journal Article
TL;DR: In this paper, a field experiment was carried out in the experimental field of Horticulture department, IGKV, Raipur (Chhattisgarh) during the year 2003-2006.
Abstract: Field experiment was carried out in the experimental field of Horticulture department, IGKV, Raipur (Chhattisgarh) during the year 2003–2006. The experiment was laid out in Randomized Block Design with four treatments i.e. 1) Red plastic mulch, 2) Black plastic mulch, 3) White plastic mulch and 4) Surface irrigation without mulch was treated as control (recommended cultivation). The experiment was laid out to assess their importance as mulching component in Tomato cultivation. The study revealed that drip irrigation with red plastic mulch of 25-micron thickness showed superior yield and yield attributing characters as compared to other mulched treatments. The yield of tomato in red plastic mulch, black plastic mulch, white plastic mulch and control plots were 335.75, 324.62 312.18 and 230.72 q/ha respectively. These results showed that the red, black and white plastic mulch increased the yield of tomato by 45.52, 40.06 and 35.30% respectively over the control. The vegetative growth flowering and quality parameters were best under red-mulched plants as camped to control. Water use efficiency and water savings were found to be highest under red plastic mulch and lowest under non-mulch condition. The net income was recorded higher under red plastic mulch (Rs.85800) and lowest in without plastic mulch (Rs. 38020). Similarly benefit cost ratio was also recorded most economical in red plastic mulch as compared to non-mulch condition.

12 citations


Proceedings ArticleDOI
18 Aug 2010
TL;DR: A current-mode signalling scheme for bidirectional long on-chip interconnects that improves the delay and power-delay product improve by 18% and 3.7×, respectively, compared to simulation results of the voltage-mode scheme.
Abstract: This paper presents a current-mode signalling scheme for bidirectional long on-chip interconnects. The transceiver has been fabricated in 180nm CMOS process. Features of the proposed scheme are driver pre-emphasis and low impedance termination. While no extra repeater is needed for line lengths up to 8mm long the scheme improves the delay by 34% for 2mm-8mm long lines, compared to bidirectional voltage-mode links. The scheme also improves the power performance for line lengths longer than 2mm, operating at data rates higher than 180Mbps. Measurement results show that delay and power-delay product improve by 18% and 3.7x, respectively, compared to simulation results of the voltage-mode scheme.

10 citations


Patent
17 Nov 2010
TL;DR: In this article, a slew rate improved operational amplifier circuit is provided to improve the slew rates of an operational amplifier with minimal sacrifices in power dissipation and other operational amplifier parameters, where additional current sources are activated when a slewing operation is detected.
Abstract: A slew rate improved operational amplifier circuit is provided to improve the slew rates of an operational amplifier with minimal sacrifices in power dissipation and other operational amplifier parameters. To improve the slew rates of operational amplifiers, additional current sources are activated when a slewing operation is detected. The detection of slewing operations and the activation of current sources upon detection can be implemented using two comparator circuits—one for a positive slewing operation, and one for a negative slewing operation. A sub-45 nm FinFET implementation of this slew rate improvement concept was implemented and compared against slew rate optimized individual two-stage operational amplifiers. Simulations show that slew rates were significantly improved by the implementation of the comparator circuits (5590 V/μs vs. 273 V/μs), with minimal increases in power dissipation (78 μW vs. 46 μW).

5 citations


Patent
14 Dec 2010
TL;DR: In this paper, a system, method and apparatus for monitoring cardiac activities of users have been disclosed, which includes a wearable and self contained cardiac activity monitoring device which operates in multiple modes.
Abstract: A system, method and apparatus for monitoring cardiac activities of users have been disclosed. The cardiac activity monitoring system proposed by the present invention includes a wearable and self contained cardiac activity monitoring device which operates in multiple modes. In one of the modes the device wirelessly transmits the recorded electrocardiogram readings to a remote communication device(s). In another mode the device has the capability to store the measured readings continuously thereby functioning as a Holter. Additionally, the device includes an ambulatory monitoring means to monitor the physical status of a user. The ambulatory readings along with the electrocardiogram readings enable physicians / doctors to trace the cardiac activities effectively and perform prognosis of an ailment.

4 citations


Proceedings ArticleDOI
22 Mar 2010
TL;DR: Several representative digital and analog circuits like buffer chain, SRAM cell, two-stage Miller Op-Amp, three-stage low-voltage Op- amp, temperature compensated current reference and Miller OTA are optimized by considering PVT variations using Auto-BET-AMS.
Abstract: In this paper, we present Auto-BET-AMS, an automated device, circuit and system-level simulation platform suitable for benchmarking emerging technologies at the end of the CMOS roadmap. This platform is suitable for technologists and circuit designers alike. One of the features of Auto-BETAMS is that no advanced knowledge of device and circuit design is needed to perform a fair evaluation of emerging technologies. To enable this, the platform comes with a versatile multi-variable optimizer that can be used to quickly optimize devices and circuits for a set of specifications. Using Auto-BET-AMS it is possible to accurately design digital and analog circuits and assess them in conventional and emerging technologies. The platform can handle definitions of charge-based devices in either the compact model form or a look-up table form. The latter is needed for devices which do not have mature compact models developed for them. Several representative digital and analog circuits like buffer chain, SRAM cell, two-stage Miller Op-Amp, three-stage low-voltage Op-Amp, temperature compensated current reference and Miller OTA are optimized by considering PVT variations using Auto-BET-AMS. Additionally, the impact of parametric variations on these circuits is studied.