D
Dongho Lee
Researcher at IBM
Publications - 4
Citations - 46
Dongho Lee is an academic researcher from IBM. The author has contributed to research in topics: Sense amplifier & Memory cell. The author has an hindex of 4, co-authored 4 publications receiving 44 citations. Previous affiliations of Dongho Lee include Lockheed Martin Corporation.
Papers
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Journal ArticleDOI
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
Gregory J. Fredeman,Donald W. Plass,Abraham Mathews,Janakiraman Viraraghavan,Kenneth J. Reyer,Thomas J. Knips,Thomas R. Miller,Elizabeth L. Gerhard,Dinesh Kannambadi,Chris Paone,Dongho Lee,Daniel J. Rainey,Michael A. Sperling,Michael Whalen,Steven Burns,Rajesh R. Tummuru,Herbert L. Ho,Alberto Cestero,Norbert Arnold,Babar A. Khan,Toshiaki Kirihata,Subramanian S. Iyer +21 more
TL;DR: A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 μm2 deep-trench capacitor cell that enables a high voltage gain of a power-gated inverter at mid-level input voltage.
Patent
Method and circuit for dynamic read margin control of a memory array
M. Canada,Stephen Frank Geissler,Robert M. Houle,Dongho Lee,Vinod Ramadurai,Mathew I. Ringler,Gerard M. Salem,Timothy J. VonReyn +7 more
TL;DR: In this paper, the authors propose a method and circuit for adjusting the read margin of a self-timed memory array, including a memory cell array including a sense amplifier self-time decode circuit adapted to set a base read time delay of the memory array.
Patent
Memory device having reduced power requirements and associated methods
TL;DR: In this paper, a memory device includes a plurality of memory cells arranged in rows and columns, and a respective bit line precharge circuit is associated with each of the plurality of sub-arrays.
Proceedings ArticleDOI
17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access
Gregory J. Fredeman,Donald W. Plass,Abraham Mathews,Kenneth J. Reyer,Thomas J. Knips,Thomas R. Miller,Elizabeth L. Gerhard,Dinesh Kannambadi,Chris Paone,Dongho Lee,Daniel J. Rainey,Michael A. Sperling,Michael Whalen,S. Burns +13 more
TL;DR: This 22nm design style has been migrated into a 14nm FinFET learning vehicle, complete with an ABIST engine, wordline charge pumps (VPP and VWL), and padcage interface circuitry.