Babar A. Khan

TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.

TL;DR: In this paper, the SOI layer is placed directly on top of a buried oxide layer, and a bottle-shaped trench is formed by etching the base substrate exposed in the lower portion of the deep trench selective to the dielectric material and the buried oxide layers.

TL;DR: In this article, the authors describe a 500MHz random cycle Silicon on Insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over traditional array design methods.

TL;DR: An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time.

TL;DR: A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces performance-enhancing 3T micro sense amplifier architecture (muSA), which confirms 1.5ns random access time with a 1V supply at 85deg and low voltage operation with a 600mV supply.