E
Elena I. Vatajelu
Researcher at Polytechnic University of Turin
Publications - 32
Citations - 381
Elena I. Vatajelu is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Static random-access memory & Magnetoresistive random-access memory. The author has an hindex of 11, co-authored 26 publications receiving 333 citations. Previous affiliations of Elena I. Vatajelu include Polytechnic University of Catalonia & University of Montpellier.
Papers
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Journal ArticleDOI
Domino logic designs for high-performance and leakage-tolerant applications
TL;DR: Several domino logic circuit techniques to improve the robustness and performance along with leakage power are proposed and lower total power consumption is achieved by utilizing proposed techniques.
Journal ArticleDOI
STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability
Elena I. Vatajelu,Giorgio Di Natale,Mario Barbareschi,Lionel Torres,Marco Indaco,Paolo Prinetto +5 more
TL;DR: This article proposes an innovative PUF design based on STT-MRAM memory that exploits the high variability affecting the electrical resistance of the Magnetic Tunnel Junction (MTJ) device in anti-parallel magnetization and demonstrates that the proposed solution is robust, unclonable, and unpredictable.
Proceedings ArticleDOI
Nonvolatile memories: Present and future challenges
TL;DR: An overview of device level operation of these nonvolatile memories, with special emphasis on the fabrication-and aging-induced reliability issues is presented.
Proceedings ArticleDOI
STT MRAM-Based PUFs
TL;DR: This paper exploits the high variability affecting the electrical resistance of the MTJ device in anti-parallel magnetization to propose an innovative design based on STT-MRAM memory that is robust, unclonable and unpredictable.
Proceedings ArticleDOI
Towards a highly reliable SRAM-based PUFs
TL;DR: This paper defines an effective method to identify the unreliable cells in the PUF implementation based on SRAM stability test to significantly reduce the need for complex ECCs resulting in efficient, low cost PUF implementations.