We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 mm2 while consuming 5 μW and achieving 4.9 μVrms of input-referred noise in a 10 kHz bandwidth.

A 0.013 ${\hbox {mm}}^{2}$ , 5 $\mu\hbox{W}$ , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

The use of a VCO-based integrator and quantizer within a continuous-time (CT) ΔΣ analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$ m CMOS

Recent success in brain-machine interfaces has provided hope for patients with spinal-cord injuries, Parkinson's disease, and other debilitating neurological conditions [1], and has boosted interest in electronic recording of cortical signals State-of-the-art recording solutions [2–5] rely heavily on analog techniques at relatively high supply voltages to perform signal conditioning and filtering, leading to large silicon area and limited programmability We present a neural interface in 65nm CMOS and operating at a 05V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller These results are achieved by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic The use of 65nm CMOS eases integration with low-power digital systems, while the low supply voltage makes the design more compatible with wireless powering schemes [6]

A 0.013mm 2 5μW DC-coupled neural signal acquisition IC with 0.5V supply

Tunnel FET technology: A reliability perspective

Since Moore’s law driven scaling of planar MOSFETs
faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing
to the presence of multiple (two/three) gates, FinFETs/Trigate
FETs are able to tackle short-channel effects (SCEs) better than
conventional planar MOSFETs at deeply scaled technology nodes
and thus enable continued transistor scaling. In this paper, we
review research on FinFETs from the bottommost device level
to the topmost architecture level. We survey different types of
FinFETs, various possible FinFET asymmetries and their impact,
and novel logic-level and architecture-level tradeoffs offered by
FinFETs. We also review analysis and optimization tools that
are available for characterizing FinFET devices, circuits, and
architectures.

/pdf/finfets-from-devices-to-architectures-3wvjf3zgcz.pdf

FinFETs: From Devices to Architectures

This paper describes a novel technique for implementing ultra low-voltage/low-power digital circuits The effective threshold voltage seen from a control gate is adjusted during a UV-light-activated tuning procedure The optimal effective threshold voltage matching the supply voltage and speed may be programmed by UV light through an activated conductance between the power rails and the floating gates Measured results are provided for gates operating down to 04-V power supply, using a standard double-poly CMOS process

Ultra low-voltage/low-power digital floating-gate circuits

We report a direct-RF pulse-based radar System on Chip (SoC) with applications in vital signs monitoring and occupancy detection. The transmitter complies with FCC, ETSI, and KCC regulatory masks with −10 dB bandwidths of 1.4 and 1.5 GHz centered at 7.29 and 8.748 GHz. The receiver samples the reflected signal at 23.328 GS/s, covering a 9.9-m consecutive range. The measured front-end noise figure is 6.3 dB with 14.7-dB gain at 7.29 GHz. Chest movements from breathing and heartbeats in a human subject were detected at 9 and 5 m, respectively. All required power management and clock functions are integrated on-chip. The SoC was implemented in 55-nm CMOS. In active mode, the system consumes 118 mW from a 1.8-V power supply.

A 118-mW Pulse-Based Radar SoC in 55-nm CMOS for Non-Contact Human Vital Signs Detection

We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device structure leads to unequal currents for positive and negative drain biases, which is exploited to achieve mitigation of read-write conflict in 6T SRAMs. The proposed device exhibits superior short-channel characteristics compared to a conventional FinFET due to reduced electric fields from the terminal that has a lower doping. This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM. Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%-8.3% improvement in read static noise margin (SNM), 4.1%-10.2% higher write margin, 4.1%-8.8% lower write time, 1.3%-3.5% higher hold SNM, and 2.1-2.5 lower cell leakage at the cost of 20%-23% higher access time. There is no area penalty associated with the proposed technique.

Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

Domino logic designs for high-performance and leakage-tolerant applications

This paper presents two novel methods for sampling the backscatter in an impulse radar system. The authors have called the two related methods for swept threshold and stochastic resonance sampling. The samplers are simple, mostly digital circuits which are not clocked, but instead utilize continuous-time signal processing. Since fine-pitch CMOS is not very good for analog processing, but instead has very fast digital logic, the samplers are well suited for this technology. An implementation in 90 nm CMOS is described and measurements which confirm a working 23 GHz sampler are shown

Dag T. Wisland

Papers

Ultra low-voltage/low-power digital floating-gate circuits

A 118-mW Pulse-Based Radar SoC in 55-nm CMOS for Non-Contact Human Vital Signs Detection

Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

Domino logic designs for high-performance and leakage-tolerant applications

Thresholded samplers for UWB impulse radar