The fifth edition of "Numerical Methods for Engineers" continues its tradition of excellence. Instructors love this text because it is a comprehensive text that is easy to teach from. Students love it because it is written for them--with great pedagogy and clear explanations and examples throughout. The text features a broad array of applications, including all engineering disciplines. The revision retains the successful pedagogy of the prior editions. Chapra and Canale's unique approach opens each part of the text with sections called Motivation, Mathematical Background, and Orientation, preparing the student for what is to come in a motivating and engaging manner. Each part closes with an Epilogue containing sections called Trade-Offs, Important Relationships and Formulas, and Advanced Methods and Additional References. Much more than a summary, the Epilogue deepens understanding of what has been learned and provides a peek into more advanced methods. Approximately 80% of the end-of-chapter problems are revised or new to this edition. The expanded breadth of engineering disciplines covered is especially evident in the problems, which now cover such areas as biotechnology and biomedical engineering. Users will find use of software packages, specifically MATLAB and Excel with VBA. This includes material on developing MATLAB m-files and VBA macros.

Numerical methods for engineers

Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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FPGA Architecture: Survey and Challenges

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

International Symposium on Quality Electronic Design

In battery-powered embedded systems, the limit of battery charge creates a challenge in scheduling tasks to meet both their deadlines and Quality of Service (QoS) requirements. Harvesting energy from the surrounding environment continuously eliminates the concern of limited battery charge. However, the uncertainty in availability of energy brings challenges in embedded systems. In this paper, we propose an energy management technique to maximize QoS of the system. Our technique is composed of two steps: an offline step and an online step. In the offline step we use frame-based energy harvesting prediction in one harvesting period, in order to find the best QoS level for the tasks and maximize the energy utilization. The information provided from the offline step guides the online scheduler to decide about job scheduling at run-time to minimize the QoS violation. We compared our scheduler with other approaches and on average we reduce the violation count by 22%.

Energy Budget Management for Energy Harvesting Embedded Systems

This paper presents a theoretical framework that solves optimally and in polynomial time many open problems in time budgeting. The approach unifies a large class of existing time-management paradigms. Examples include time budgeting for maximizing total weighted delay relaxation, minimizing the maximum relaxation, and min-skew time budget distribution. The authors develop a combinatorial framework through which we prove that many of the time-management problems can be transformed into a min-cost flow problem instance. The methodology is applied to intellectual-property-based datapath synthesis targeting field-programmable gate arrays. The synthesis flow maps the input operations to parameterized library modules during which different time budgeting policies have been applied. The techniques always improve the area requirement of the implemented test benches and consistently outperform a widely used competitor. The experiments verify that combining fairness and maximization objectives improves the results further as compared with pure maximum budgeting. The combined fairness and maximization objective improves the area by 25.8% and 28.7% in slice and LUT counts, respectively

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A Unified Theory of Timing Budget Management

The pervasiveness of heterogeneous multiprocessors (HMP) in the mobile domain enables more energy efficient systems. However, current approaches to exploit the energy efficiency of HMPs results in unbalanced usage of resources, which leads to higher aging rates and delay degradation when compared to homogeneous architectures. In this paper, we propose ADAMANt , an aging-aware task mapping algorithm for HMPs. ADAMANt exploits on-chip sensing of aging, performance, and power in order to enable on-line workload characterization to select task-to-core mappings that yield both increased system lifetime and energy efficiency. Experimental evaluation using a typical mobile workload demonstrates an improvement in chip lifetime by up to 2 $\times$ on a big.LITTLE architecture.

Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile Platforms

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Due to advanced silicon technology, reconfigurable system-on-chip devices such as FPGAs are increasingly becoming sensitive to aging effects. This paper presents a high-level physical planning with reconfiguration strategy in order to mitigate the aging-induced delay degradation in FPGA resources. The proposed solution is an offline framework composed of an aging-aware floorplanner coupled with a proactive aging-aware reconfiguration policy which generates checkpoints aperiodically for runtime reconfiguration. We consider BTI and HCI aging mechanisms and consider the BTI-based aging recovery during idle periods using aging history map. The experiments demonstrate that sequence of configurations generated by this scheme provides average aging-rate reduction on FPGA resources and application performance by 53.2% and 17.5%, respectively.

Eli Bozorgzadeh

Papers

Energy Budget Management for Energy Harvesting Embedded Systems

A Unified Theory of Timing Budget Management

Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile Platforms

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Aging-aware high-level physical planning for reconfigurable systems