The fifth edition of "Numerical Methods for Engineers" continues its tradition of excellence. Instructors love this text because it is a comprehensive text that is easy to teach from. Students love it because it is written for them--with great pedagogy and clear explanations and examples throughout. The text features a broad array of applications, including all engineering disciplines. The revision retains the successful pedagogy of the prior editions. Chapra and Canale's unique approach opens each part of the text with sections called Motivation, Mathematical Background, and Orientation, preparing the student for what is to come in a motivating and engaging manner. Each part closes with an Epilogue containing sections called Trade-Offs, Important Relationships and Formulas, and Advanced Methods and Additional References. Much more than a summary, the Epilogue deepens understanding of what has been learned and provides a peek into more advanced methods. Approximately 80% of the end-of-chapter problems are revised or new to this edition. The expanded breadth of engineering disciplines covered is especially evident in the problems, which now cover such areas as biotechnology and biomedical engineering. Users will find use of software packages, specifically MATLAB and Excel with VBA. This includes material on developing MATLAB m-files and VBA macros.

Numerical methods for engineers

Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

/pdf/fpga-architecture-survey-and-challenges-n7zq0kh5x3.pdf

FPGA Architecture: Survey and Challenges

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

International Symposium on Quality Electronic Design

Due to decreasing transistor sizes and increasing clock frequency, interconnect delay is a dominant factor in achieving timing closure in deep sub-micron designs. Techniques like wire pipelining and retiming can manage delay of timing critical wires. The latency of the system, however, limits the total pipelining in the design. New techniques are, thus, needed at synthesis stage to consider the effect of critical wires in the design. In this work, we propose a novel intuitive algorithm, critical edge reduction (CER) algorithm, which produces a maximal delay budgeting solution under fixed latency while minimizing the number of critical wires. We also present an in-depth analysis of trade-off between maximum budgeting and critical edge minimization. We implemented our design flow using a set of MediaBench data paths on Xilinx VirtexE FPGA devices. Using our algorithm, the Xilinx Place and Route tool achieved timing closure, on average, 2.8 times faster than using maximum budgeting. The resulting average clock period using CER algorithm outperforms the one using maximum budgeting by 6%.

/pdf/fast-timing-closure-by-interconnect-criticality-driven-delay-4y9127wnvh.pdf

Fast timing closure by interconnect criticality driven delay relaxation

Energy harvesting from environments such as solar energy are promising solutions to tackle energy sustainability in embedded systems. However, uncertainties in energy availability, non-ideal characteristics of harvesting circuits, energy storage (battery or supercapacitor), and application demand dynamics add more complexity in the system. We present a unified model based on discrete-time Finite State Markov Chain to capture the dynamicity and variations in both the energy supply from solar irradiance and the energy demand from the application. In this paper, we exploit the temporal and spatial characteristics of solar energy and propose a deterministic profile with stochastic process to reflect the fluctuation due to unexpected weather condition. Optimal policy to maximize expected total QoS is derived from the presented model using a probabilistic dynamic programming approach. Compared to a state-of-the-art deterministic energy management framework, our proposed approach outperforms in term of QoS and energy sustainability (with less shutdown time) of the system.

/pdf/a-unified-stochastic-model-for-energy-management-in-solar-2q8p2qwzc6.pdf

A Unified Stochastic Model for Energy Management in Solar-Powered Embedded Systems

Computer vision algorithms are computationally expensive and difficult to implement efficiently. Field Programmable Gate Arrays (FPGA)s offer a promising direction to reduce the computation cost by exploiting hardware parallelism. However, it is difficult to translate vision algorithms to FPGA bitstream efficiently. OpenVX is an industry standard for graph-based representation of vision algorithms. It defines a set of widely used vision kernels and data structures that can be used to form a Directed Acyclic Graph (DAG) to represent a vision algorithm. This paper proposes a framework for automatic FPGA acceleration of computer vision algorithms based on OpenVX specification, called AFFIX. AFFIX receives a vision algorithm formed using the OpenVX and generates a heterogeneous CPU-FPGA implementation. AFFIX incorporates several high level and low-level optimization methods to improve the efficiency of the FPGA implementation. It provides a configurable and extensible framework that enables vision algorithm developers to quickly develop, verify and test FPGA implementations of vision algorithms. We demonstrate the effectiveness of the proposed framework via development and evaluations of multiple vision algorithms.

AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms

On leakage power optimization in clock tree networks for ASICs and general-purpose processors

Energy storage is a fundamental component for the development of sustainable and environment-aware technologies. One of the critical challenges that needs to be overcome is preserving the State of Health (SoH) in energy harvesting systems, where bursty arrival of energy and load may severely degrade the battery. Tools from Markov process and Dynamic Programming theory are becoming an increasingly popular choice to control dynamics of these systems due to their ability to seamlessly incorporate heterogeneous components and support a wide range of applications. Mapping aging rate measures to fit within the boundaries of these tools is non-trivial. In this paper, a framework for modeling and controlling the aging rate of batteries based on Markov process theory is presented. Numerical results illustrate the tradeoff between battery degradation and task completion delay enabled by the proposed framework.

Eli Bozorgzadeh

Papers

Fast timing closure by interconnect criticality driven delay relaxation

A Unified Stochastic Model for Energy Management in Solar-Powered Embedded Systems

AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms

On leakage power optimization in clock tree networks for ASICs and general-purpose processors

Modeling And Control Battery Aging in Energy Harvesting Systems