Showing papers by "Emmanuel Dubois published in 2006"
01 Dec 2006
TL;DR: In this article, the authors present new results on silicon I-MOS devices, obtained by an adaptation of a conventional CMOS process, where the source and the drain are doped of opposite type.
Abstract: This papers presents new results on silicon I-MOS devices, (where the source and the drain are doped of opposite type) obtained by an adaptation of a conventional CMOS process. Fabricated devices are fully functional down to 55nm of gate length, but the influence of the gate becomes strongly reduced for shorter devices due to technological limitations. Nevertheless, the smallest device, with a 17nm gate length and with an avalanche threshold of 5.3V, is reported. The corresponding output current-voltage features an equivalent resistance as low as 66 Omegamiddotmum. For all devices, the maximum current is only limited by the contacts destruction, positioning the measured value of 4700 muA/mum among the highest ever reported for a MOS device. In addition, it is shown that the extrapolated Ion/Ioff figure of merit is close to complying with the specifications imposed to the HP flavor of the ITRS'05 roadmap
28 citations
TL;DR: In this paper, the impact of the pre-exposure bake temperature, of the Tetramethyl ammonium hydroxide (TMAH) concentration in development solution and of development time has been investigated.
11 citations
TL;DR: In this paper, a self-aligned single-dot memory device and arrays were fabricated based on arsenic-assisted etching and oxidation effects, with a floating gate of about 5-10 nm, presenting single-electron memory operation at room temperature.
Abstract: Self-aligned single-dot memory devices and arrays were fabricated based on arsenic-assisted etching and oxidation effects. The resulting device has a floating gate of about 5-10 nm, presenting single-electron memory operation at room temperature. In order to realize the final single-electron memory circuit, this paper investigates process repeatability, device uniformity in single-dot memory arrays, device scalability, and process transferability to an industrial application
10 citations
01 Dec 2006-Nuclear Instruments & Methods in Physics Research Section B-beam Interactions With Materials and Atoms
TL;DR: In this article, the formation process of the Pt/Si structure of low Schottky barrier MOSFETs on SOI was investigated and diffraction analysis showed that only the PtSi orthorhombic phase is formed in all studied samples.
Abstract: We report investigations of the silicide formation process in the Pt/Si structure of low Schottky barrier MOSFETs on SOI. The silicide layers are used there as source and drain contacts and the high quality of the silicide/Si interface and the silicide structure are essential for the electrical properties of the device. The platinum silicide is formed by the solid-state reaction between 15 nm thick Pt metallisation and a Si substrate during the annealing by the rapid-thermal-annealing (RTA) process at various temperatures (300, 400 and 500 °C). Cross-sectional transmission electron microscopy (XTEM) specimens were used to study the formation of the platinum silicide. The studies enabled the determination of the silicide layer thickness and morphology, as well as the silicide/Si interface roughness. The silicide layer for all investigated temperatures consists of a single layer of the silicide grains placed side by side. After annealing at 300 °C the grains are irregular in shape, while after 400 °C the shapes of the most of grains are regular, visible as squares or rectangles in a cross-section. After annealing at 500 °C the elongated grains due to the grain coalescence are mostly observed. The thickness of the silicide layer after annealing at 300 and 400 °C is about 29–30 nm. After annealing at 500 °C, the thickness changes and equals from about 27–28 nm at grain boundaries, to about 32–35 nm in the middle of grains. The roughness of the silicide/Si interface increases with the annealing temperature. The diffraction techniques were used to identify the silicide phase. The diffraction analysis showed that only the PtSi orthorhombic phase is formed in all studied samples.
9 citations
22 Oct 2006
TL;DR: A new prototyping approach is presented: a combination of model-based design and simulation based prototyping for mixed reality systems.
Abstract: Development of mixed reality systems is almost always following an ad-hoc process. The development cycle often turns out to be highly expensive and time consuming. This paper presents a new prototyping approach: a combination of model-based design and simulation based prototyping.
8 citations
18 Apr 2006
TL;DR: This paper shows the different steps of a co-design process dedicated to build augmented interactive experiments in Museums, which enables an analytic framework listing the different dimensions to tackle during the design of augmented interactions.
Abstract: This paper shows the different steps of a co-design process dedicated to build augmented interactive experiments in Museums. This process enables an analytic framework listing the different dimensions to tackle during the design of augmented interactions. These different steps are illustrated by a case of study in the classification of life.
6 citations
TL;DR: In this paper, a negative tone e-beam resist is used to limit the impact of proximity effects on the performance of the HSQ resist in the pre-and post-e-beam exposure process.
6 citations
01 Sep 2006
TL;DR: In this paper, a new process to realize impact ionization MOSFETs (I-MOS) with gate length down to 50nm is reported, which assures a perfect compatibility with conventional CMOS.
Abstract: This paper reports on a new process to realize impact-ionization MOSFETs (I-MOS) with gate length down to 50nm. This process is an adaptation of a standard 90nm flow, which assures a perfect compatibility with conventional CMOS. The definition of the n+ and p+ regions of the I-MOS is based on two shifted lithography steps using the standard source/drain mask. An analytical model for the breakdown voltage of an ID p-i-n diode has also been developed to express the breakdown voltage of I-MOS devices as a function of the gate and intrinsic lengths, and the doping level. This model has been validated by the experimental results. An extremely low experimental device resistance (270 Omega.mum) is reported at a gate length of 55 nm, placing the I-MOS architecture favorably with respect to ITRS requirements. This performance is explained by the much higher carrier concentration generated by impact ionization when compared to the conventional MOS. Channel resistance is found negligible and current only limited by the source/drain (S/D) resistance
5 citations
13 Mar 2006
TL;DR: In this article, the influence of the gate spacer offset width (L/sub offset) on SOI MOSFET high frequency (HF) properties was investigated, and the DC simulated results were calibrated on experimental data of a 130 nm SOI partially depleted technology.
Abstract: This work focuses on the influence of the gate spacer offset width (L/sub offset/) on SOI MOSFET high frequency (HF) properties. For this purpose, the DC simulated results were calibrated on experimental data of a 130 nm SOI partially depleted technology. Variations of L/sub offset/ were subsequently applied to study its impact on different HF figures of merit (f/sub t/, f/sub max/).
4 citations
Journal Article•
3 citations
18 Apr 2006
TL;DR: This process supports the systematic exploration of mixed interaction design solutions and offers a framework to present data collected in a Focus-Group and connects to an existing tool for the design of mixed systems.
Abstract: This paper introduces and illustrates a process that integrates Focus-Group into early phases of a mixed systems design process. This process supports the systematic exploration of mixed interaction design solutions and offers a framework to present data collected in a Focus-Group. We also present a connection between this process and an existing tool for the design of mixed systems.
TL;DR: Very thin erbium silicide layers have been used as source and drain contacts to n‐type Si in low Schottky barrier MOSFETs on silicon‐on‐insulator substrates and constitute proof that Si reacts with Er in the presence of a Pt top layer in the temperature range 450–600 °C.
Abstract: Very thin erbium silicide layers have been used as source and drain contacts to n-type Si in low Schottky barrier MOSFETs on silicon-on-insulator substrates Erbium silicide is formed by a solid-state reaction between the metal and silicon during annealing The influence of annealing temperature (450 degrees C, 525 degrees C and 600 degrees C) on the formation of an erbium silicide layer in the Pt/Er/Si/SiO2/Si structure was analysed by means of cross-sectional transmission electron microscopy The Si grains/interlayer formed at the interface and the presence of Si grains within the Er-related layer constitute proof that Si reacts with Er in the presence of a Pt top layer in the temperature range 450-600 degrees C The process of silicide formation in the Pt/Er/Si structure differs from that in the Er/Si structure At 600 degrees C, the Pt top layer vanishes and a (Pt-Er)Si-x system is formed
14 Aug 2006
TL;DR: In this paper, the Schottky-Barrier (SB) MOSFETs that feature platinum silicide (PtSi) source/drain and a tungsten midgap gate down to a length of 40 nm were shown to steadily progress with respect to conventional highly-doped S/D with a current drive (I on ) of 325-425 μA/μm, an off-state current (I off ) of 14-368 nA/m at -2V for 100-40 nm physical gate lengths.
Abstract: This paper demonstrates the successful integration of Schottky-Barrier (SB) MOSFETs that feature platinum silicide (PtSi) source/drain and a tungsten midgap gate down to a length of 40 nm. SB-MOSFETs are shown to steadily progress with respect to conventional highly-doped S/D with a current drive (I on ) of 325-425 μA/μm, an off-state current (I off ) of 14-368 nA/μm at -2V for 100-40 nm physical gate lengths, respectively.