Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

A prevalent and pervasive view of designing is that it can be modeled using variables and decisions made about what values should be taken by these variables. The activity of designing is carried out with the expectation that the designed artifact will operate in the natural world and the social world. These worlds impose constraints on the variables and their values; so, design could be described as a goal-oriented, constrained, decision- making activity. However, design distinguish- es itself from other similarly described activities not only by its domain but also by additional necessary features. Designing involves exploration, exploring what variables might be appropriate. The process of explo- ration involves both goal variables and deci- sion variables. In addition, designing involves learning: Part of the exploration activity is learning about emerging features as a design proceeds. Finally, design activity occurs within two contexts: the context within which the designer operates and the context produced by the developing design itself. The designer’s perception of what the context is affects the implication of the context on the design. The context shifts as the designer’s perceptions change. Design activity can be now characterized as a goal-oriented, con- strained, decision-making, exploration, and learning activity that operates within a con- text that depends on the designer’s percep- tion of the context.

Design Prototypes: A Knowledge Representation Schema for Design

Creativity: Flow and the Psychology of Discovery and Invention

Cognitive engineering

Thanks to their large surface-to-volume ratio, silicon nanowires (Si NWs) are extremely sensitive to all phenomena which could alter their surface potential and charge distribution. Those surface variations lead to a change of the Si NWs equivalent conductance. The use of the output conductance of a silicon nanowire as a compact transducer for direct detection of (bio)chemical molecules or gases has gained immense attention these last years. In this paper, fabrication of silicon nanowires using top-down approach is shown, with simple calculations to determine hole mobility, hole concentration and resistivity. Transfer characteristics and sampling measurements were performed on the nanowires with and without surface functionalization under various ambient conditions indicating the importance of functionalization in order to avoid any environment effect on the transport properties of the nanowires.

Functionalization of Silicon Nanowires for Specific Sensing

This paper reports on a new process to realize impact-ionization MOSFETs (I-MOS) with gate length down to 50nm. This process is an adaptation of a standard 90nm flow, which assures a perfect compatibility with conventional CMOS. The definition of the n+ and p+ regions of the I-MOS is based on two shifted lithography steps using the standard source/drain mask. An analytical model for the breakdown voltage of an ID p-i-n diode has also been developed to express the breakdown voltage of I-MOS devices as a function of the gate and intrinsic lengths, and the doping level. This model has been validated by the experimental results. An extremely low experimental device resistance (270 Omega.mum) is reported at a gate length of 55 nm, placing the I-MOS architecture favorably with respect to ITRS requirements. This performance is explained by the much higher carrier concentration generated by impact ionization when compared to the conventional MOS. Channel resistance is found negligible and current only limited by the source/drain (S/D) resistance

Fabrication and Analysis of CMOS Fully-Compatible High Conductance Impact-Ionization MOS (I-MOS) Transistors

3D Virtual Environments (3DVE) come up as a good solution to transmit knowledge in a museum exhibit. In such contexts, providing easy to learn and to use interaction techniques which facilitate the handling inside a 3DVE is crucial to maximize the knowledge transfer. We took the opportunity to design and implement a software platform for explaining the behavior of the Telescope Bernard-Lyot to museum visitors on top of the Pic du Midi. Beyond the popularization of a complex scientific equipment, this platform constitutes an open software environment to easily plug different 3D interaction techniques. Recently, popular use of a smartphones as personal handled computer lets us envision the use of a mobile device as an interaction support with these 3DVE. Accordingly, we design and propose how to use the smartphone as a tangible object to navigate inside a 3DVE. In order to prove the interest in the use of smartphones, we compare our solution with available solutions: keyboard-mouse and 3D mouse. User experiments confirmed our hypothesis and particularly emphasizes that visitors find our solution more attractive and stimulating. Finally, we illustrate the benefits of our software framework by plugging alternative interaction techniques for supporting selection and manipulation task in 3D.

https://hal.archives-ouvertes.fr/hal-01387801/document

Smartphone Based 3D Navigation Techniques in an Astronomical Observatory Context: Implementation and Evaluation in a Software Platform

A fast one-dimensional (1-D) numerical model suitable for circuit analysis has been developed for fully-depleted silicon-on-insulator MOSFETs. The novel important feature of our CAD-oriented approach consists in a rigorous treatment of the nonquasistatic charge redistribution that ensures accuracy under fast switching conditions. The capabilities of this model are exemplified through the simulation of an analog transmission gate to evaluate the impact of charge sharing effects.

Nonquasistatic transient model of fully-depleted SOI MOSFET and its application to the analysis of charge sharing in an analog switch

Schottky-barrier source/drain (S/D) MOSFETs (SB-MOS) have recently demonstrated leading edge high frequency (HF) performance, featuring a 280 GHz current gain cut-off frequency fT at 30 nm of gate length. Although this figure represents the best ever recorded fT for a p-MOSFET, little effort has been produced, so far, to analyze key small signal elements (SSE) such as the transconductance G m and the total input capacitance Cgg that directly impact fT. This work demonstrates that the loss of transconductance related to the Schottky barrier (SB) is counterbalanced by a reduction of the total gate capacitance

Emmanuel Dubois

Papers

Functionalization of Silicon Nanowires for Specific Sensing

Fabrication and Analysis of CMOS Fully-Compatible High Conductance Impact-Ionization MOS (I-MOS) Transistors

Smartphone Based 3D Navigation Techniques in an Astronomical Observatory Context: Implementation and Evaluation in a Software Platform

Nonquasistatic transient model of fully-depleted SOI MOSFET and its application to the analysis of charge sharing in an analog switch

Investigation of High Frequency Performance for Schottky-Barrier p-MOSFET