Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

A prevalent and pervasive view of designing is that it can be modeled using variables and decisions made about what values should be taken by these variables. The activity of designing is carried out with the expectation that the designed artifact will operate in the natural world and the social world. These worlds impose constraints on the variables and their values; so, design could be described as a goal-oriented, constrained, decision- making activity. However, design distinguish- es itself from other similarly described activities not only by its domain but also by additional necessary features. Designing involves exploration, exploring what variables might be appropriate. The process of explo- ration involves both goal variables and deci- sion variables. In addition, designing involves learning: Part of the exploration activity is learning about emerging features as a design proceeds. Finally, design activity occurs within two contexts: the context within which the designer operates and the context produced by the developing design itself. The designer’s perception of what the context is affects the implication of the context on the design. The context shifts as the designer’s perceptions change. Design activity can be now characterized as a goal-oriented, con- strained, decision-making, exploration, and learning activity that operates within a con- text that depends on the designer’s percep- tion of the context.

Design Prototypes: A Knowledge Representation Schema for Design

Creativity: Flow and the Psychology of Discovery and Invention

Cognitive engineering

Towards A Serious Application for Telescope Maintenance

A detailed study of the punchthrough formation mechanism induced by the walled emitter configuration is proposed. Efficient process and device simulation tools -IMPACT- have been used and results have been successfully compared to measured characteristics.

http://ieeexplore.ieee.org/iel5/5436369/5436370/05436482.pdf

Analysis of the Punchthrough Effect in Walled Emitter Bipolar Transistors

Jun Yin, Tianqi Zhu, Di Zhou, Thierno Moussa Bah, Stanislav Didenko, Severine Gomes, Olivier Bourgeois, Didier Pellerin, Emmanuel Dubois and Jean-François Robillard a. Univ. Lille, CNRS, Centrale Lille, ISEN, Univ. Valenciennes, UMR 8520-IEMN, F-59000 Lille, France b. Centre for Energy and Thermal Sciences, Lyon (CETHIL)-CNRS, INSA, UCBL, Campus La Doua LyonTech, Lyon, France c. Institut NEEL, CNRS-UJF, 25 rue des Martyrs, 38042 Grenoble, France d. CSInstruments, 2 rue de la Terre de Feu, 91940 Les ULIS, France

Nanometer-scale active thermal devices for thermal microscopy probe calibration

Spreadsheets on tablet, based on multitouch interaction is tedious and raises multiple interaction issues such as screen size or limited tactile interaction. To answer this limitations, we propose the use of the stacking paradigm, which consists in laying one edge of a smartphone on a tablet screen. It offers the double benefit of augmenting the input vocabulary and extending the display surface. We built a prototype based on a 3D printed shell augmented with copper to detect the smartphone on the tablet screen. We also developed a simplified spreadsheet app on the tablet in which users can select cells using three stacking-based interaction techniques.

/pdf/cell-selection-for-spreadsheets-on-tablets-stacking-based-ifbhzavugd.pdf

Cell Selection for Spreadsheets on Tablets: Stacking-Based Interaction

With the evolution of radio frequency (RF)/microwave technology, there is a demand for circuits which are able to meet highly challenging RF frontend specifications. Silicon-on-insulator (SOI) technology is one of the leading platforms for upcoming wireless generation. The degradation of performance due to substrate coupling is a key problem to address for telecommunication circuits, especially for the high throw count switches in RF frontends. In this context, a novel technique for local substrate removal is developed to fabricate membranes of mm-sized RF switch which allows for total etching of silicon handler. RF characterization of membranes reveal a superior linearity performance with lowering of 2 nd harmonic by 17.7 dB and improvement in insertion losses by 0.38 dB in comparison with High-Resistivity SOI substrates. This improvement leads to a significant increase in frontend efficiency. These results demonstrate a new route for optimization of circuit performance using post-fabrication substrate processing techniques.

Emmanuel Dubois

Papers

Towards A Serious Application for Telescope Maintenance

Analysis of the Punchthrough Effect in Walled Emitter Bipolar Transistors

Nanometer-scale active thermal devices for thermal microscopy probe calibration

Cell Selection for Spreadsheets on Tablets: Stacking-Based Interaction

Mitigation of substrate coupling effects in RF switch by localized substrate removal using laser processing